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ADC3683 датащи(PDF) 53 Page - Texas Instruments

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номер детали ADC3683
подробное описание детали  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 датащи(HTML) 53 Page - Texas Instruments

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Figure 9-3. Register 0x08
7
6
5
4
3
2
1
0
0
0
PDN CLKBUF
PDN REFAMP
0
PDN A
PDN B
PDN GLOBAL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-4. Register 0x08 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
PDN CLKBUF
R/W
0
Powers down sampling clock buffer
0: Clock buffer enabled
1: Clock buffer powered down
4
PDN REFAMP
R/W
0
Powers down internal reference gain amplifier
0: REFAMP enabled
1: REFAMP powered down
3
0
R/W
0
Must write 0
2
PDN A
R/W
0
Powers down ADC channel A
0: ADC channel A enabled
1: ADC channel A powered down
1
PDN B
R/W
0
Powers down ADC channel B
0: ADC channel B enabled
1: ADC channel B powered down
0
PDN GLOBAL
R/W
0
Global power down via SPI
0: Global power disabled
1: Global power down enabled. Power down mask (register
0x0D) determines which internal blocks are powered down.
Figure 9-4. Register 0x09
7
6
5
4
3
2
1
0
0
0
PDN FCLKOUT PDN DCLKOUT
PDN DA1
PDN DA0
PDN DB1
PDN DB0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-5. Register 0x09 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
PDN FCLKOUT
R/W
0
Powers down frame clock (FCLK) LVDS output buffer
0: FCLK output buffer enabled
1: FCLK output buffer powered down
4
PDN DCLKOUT
R/W
0
Powers down DCLK LVDS output buffer
0: DCLK output buffer enabled
1: DCLK output buffer powered down
3
PDN DA1
R/W
0
Powers down LVDS output buffer for channel A, lane 1.
NOT powered down automatically in 1-wire and 1/2-wire mode.
0: DA1 LVDS output buffer enabled
1: DA1 LVDS output buffer powered down
2
PDN DA0
R/W
0
Powers down LVDS output buffer for channel A, lane 0.
0: DA0 LVDS output buffer enabled
1: DA0 LVDS output buffer powered down
1
PDN DB1
R/W
0
Powers down LVDS output buffer for channel B, lane 1. NOT
powered down automatically in 1-wire and 1/2-wire mode.
0: DB1 LVDS output buffer enabled
1: DB1 LVDS output buffer powered down
0
PDN DB0
R/W
0
Powers down LVDS output buffer for channel B, lane 0.
NOT powered down automatically in 1/2-wire mode.
0: DB0 LVDS output buffer enabled
1: DB0 LVDS output buffer powered down
www.ti.com
ADC3683-SP
SBASAB5 – MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
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Product Folder Links: ADC3683-SP



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