поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

ADC3683 датащи(PDF) 63 Page - Texas Instruments

Click here to check the latest version.
номер детали ADC3683
подробное описание детали  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 датащи(HTML) 63 Page - Texas Instruments

Back Button ADC3683 Datasheet HTML 59Page - Texas Instruments ADC3683 Datasheet HTML 60Page - Texas Instruments ADC3683 Datasheet HTML 61Page - Texas Instruments ADC3683 Datasheet HTML 62Page - Texas Instruments ADC3683 Datasheet HTML 63Page - Texas Instruments ADC3683 Datasheet HTML 64Page - Texas Instruments ADC3683 Datasheet HTML 65Page - Texas Instruments ADC3683 Datasheet HTML 66Page - Texas Instruments ADC3683 Datasheet HTML 67Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 63 / 70 page
background image
Table 9-21. Register 0x26 Field Descriptions (continued)
Bit
Field
Type
Reset
Description
0
FS/4 MIX B
R/W
0
Enables FS/4 mixing for DDC B (complex decimation only).
0: FS/4 mixing disabled.
1: FS/4 mixing enabled.
Figure 9-19. Register 0x27
7
6
5
4
3
2
1
0
0
0
0
OP ORDER A
Q-DEL A
FS/4 MIX PH A
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-22. Register 0x27 Field Descriptions
Bit
Field
Type
Reset
Description
7-5
0
R/W
0
Must write 0
4
OP ORDER A
R/W
0
Swaps the I and Q output order for channel A. See Table 9-23
for recommended settings. Only used with complex decimation.
Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Output order is swapped: Q[n], I[n]
3
Q-DEL A
R/W
0
This delays the Q-sample output of channel A by one. See
Table 9-23 for recommended settings. Only used with complex
decimation. Set to 0 with real decimation.
0: Output order is I[n], Q[n]
1: Q-sample is delayed by 1 sample: I[n], Q[n+1], I[n+1], Q[n+2]
2
FS/4 MIX PH A
R/W
0
Inverts the mixer phase for channel A when using FS/4 mixer.
0: Mixer phase is non-inverted
1: Mixer phase is inverted
1-0
0
R/W
0
Must write 0
Table 9-23. OP-ORDER and Q-DELAY Register Settings for Complex Decimation
SLVDS INTERFACE
OP-ORDER
Q-DELAY
2-wire
1
0
1-wire
0
1
1/2-wire
1
1
Figure 9-20. Register 0x2A, B, C, D
7
6
5
4
3
2
1
0
NCO A [7:0]
NCO A [15:8]
NCO A [23:16]
NCO A [31:24]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 9-24. Register 0x2A, 2B, 2C, 2D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
NCO A [31:0]
R/W
0
Sets the 32 bit NCO value for decimation filter channel A. The
NCO value is fNCO× 232 / FS.
In real decimation mode, these registers are automatically set to
0.
www.ti.com
ADC3683-SP
SBASAB5 – MARCH 2024
Copyright © 2024 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: ADC3683-SP



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com