ADC3683 datasheet(47/70 Pages) TI1

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8.3 Initialization Set Up

After power-up, the internal registers must be initialized to their default values through a hardware reset by

applying a high pulse on the RESET pin, as shown in Figure 8-6.

1. Apply AVDD and IOVDD (no specific sequence required). After AVDD is applied, the internal bandgap

reference powers up and settles out in approximately 2ms.

2. Configure REFBUF pin (pull high or low even if configured via SPI later on) and apply the sampling clock.

3. Apply hardware reset. After hardware reset is released, the default registers are loaded from internal fuses

and the internal power up capacitor calibration is initiated. The calibration takes approximately 200000 clock

cycles.

4. Begin programming using SPI interface.

AVDD

IOVDD

RESET

SEN

REFBUF

Ext VREF

CLK

Figure 8-6. Initialization of serial registers after power up

Table 8-5. Power-up timing

MIN

TYP

MAX

UNIT

Power-on delay: delay from power up to logic level of

REFBUF pin

RESET pulse width

Delay from RESET disable to SEN active

~ 200000

clock cycles

8.3.1 Register Initialization During Operation

If required, the serial interface registers can be cleared and reset to default settings during operation either:

• through a hardware reset or

• by applying a software reset. When using the serial interface, set the RESET bit (D0 in register address 0x00)

high. This setting initializes the internal registers to the default values, and then self-resets the RESET bit low.

In this case, the RESET pin is kept low.

After hardware or software reset, the wait time is also approximately 200000 clock cycles before the SPI

registers can be programmed.

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ADC3683-SP

SBASAB5 – MARCH 2024

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