ADC3683 datasheet(45/70 Pages) TI1

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Table 8-1. Design Key Care-Abouts

FEATURE

DESCRIPTION

Signal Bandwidth

DC to 20MHz

Input Driver

Single ended to differential signal conversion and DC coupling

Clock Source

External clock with low jitter

When designing the amplifier or filter driving circuit, the ADC input full-scale voltage needs to be taken into

consideration. For example, the ADC3683-SP input full-scale is 3.2VPP. When factoring in approximately 1dB

for insertion loss of the filter, then the amplifier needs to deliver close to 3.6VPP. The amplifier distortion

performance degrades with a larger output swing and considering the ADC common mode input voltage the

amplifier may not be able to deliver the full swing. The device provides an output common mode voltage of

0.95V and the THS4541 for example can only swing within 250 mV of the negative supply. A unipolar 3.3V

amplifier power supply limits the maximum voltage swing to approximately 2.8VPP. Thus, if a larger output swing

is required (factoring in filter insertion loss) then a negative supply for the amplifier is needed to eliminate that

limitation. Additionally, input voltage protection diodes can be used to protect the ADC from over-voltage events.

Table 8-2. Output Voltage Swing of THS4541 vs Power Supply

DEVICE

MIN OUTPUT VOLTAGE

MAX SWING WITH 3.3V/ 0V SUPPLY

MAX SWING WITH 3.3V/ -1V SUPPLY

THS4541

VS- + 250mV

2.8VPP

6.8VPP

8.2.2 Detailed Design Procedure

8.2.2.1 Input Signal Path

Depending on desired input signal frequency range, the THS4551 and THS4541 provide a good low power

options to drive the ADC inputs. Table 8-3 provides a comparison between the THS4551 and THS4541 and the

power consumption vs usable frequency trade off.

Table 8-3. Fully Differential Amplifier Options

DEVICE

CURRENT (IQ) PER CHANNEL

USABLE FREQUENCY RANGE

THS4561

0.8mA

< 3MHz

THS4551

1.4mA

< 10MHz

THS4541

10mA

< 70MHz

The low pass filter design (topology, filter order) is driven by the application. However, when designing the low

pass filter, the optimum load impedance for the amplifier should also be taken into consideration. Between the

low pass filter and the ADC input, the sampling glitch filter needs to be added as shown in Section 7.3.1.1.1. In

this example, the DC - 30MHz glitch filter is selected.

8.2.2.2 Sampling Clock

Applications operating with low input frequencies (such as DC to 20MHz) typically are less sensitive to

performance degradation due to clock jitter. The internal ADC aperture jitter improves with faster rise and fall

times (that is, square wave vs sine wave). Table 8-4 provides an overview of the estimated SNR performance of

the device based on different amounts of jitter of the external clock source. The SNR is estimated based on the

device thermal noise of 84.2dBFS and input signal at -1dBFS.

Termination of the clock input should be considered for long clock traces.

Table 8-4. ADC SNR Performance Across vs Input Frequency for Different Amounts of External Clock

Jitter

INPUT FREQUENCY

TJ,EXT = 100fs

TJ,EXT = 250fs

TJ,EXT = 500fs

TJ,EXT = 1ps

5MHz

84.2

84.1

83.9

83.4

10MHz

84.0

83.9

83.3

81.5

20MHz

83.6

83.0

81.3

77.8

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ADC3683-SP

SBASAB5 – MARCH 2024

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