ADC3683 datasheet(55/70 Pages) TI1

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Figure 9-6. Register 0x0E

SYNC PIN EN

SPI SYNC

SPI SYNC EN

REF CTL

REF SEL

SE CLK EN

R/W-0

Table 9-7. Register 0x0E Field Descriptions

Bit

Field

Type

Reset

Description

SYNC PIN EN

R/W

This bit controls the functionality of the SYNC/PDN pin.

0: SYNC/PDN pin exercises global power down mode when pin

is pulled high.

1: SYNC/PDN pin issues the SYNC command when pin is

pulled high.

SPI SYNC

R/W

Toggling this bit issues the SYNC command using the SPI

This bit doesn't self reset to 0.

0: Normal operation

1: SYNC command issued.

SPI SYNC EN

R/W

This bit enables synchronization using SPI instead of the

SYNC/PDN pin.

0: Synchronization using SPI register bit disabled.

1: Synchronization using SPI register bit enabled.

R/W

Must write 0

REF CTL

R/W

This bit determines if the REFBUF pin controls the voltage

reference selection or the SPI register (D2-D1).

0: The REFBUF pin selects the voltage reference option.

1: Voltage reference is selected using SPI (D2-D1) and single

ended clock using D0.

2-1

REF SEL

R/W

Selects of the voltage reference option. REF CTRL (D3) must be

set to 1.

00: Internal reference

01: External voltage reference (1.2V) using internal reference

buffer (REFBUF)

10: External voltage reference

11: not used

SE CLK EN

R/W

Selects single ended clock input and powers down the

differential sampling clock input buffer. REF CRTL (D3) must be

set to 1.

0: Differential clock input

1: Single ended clock input

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ADC3683-SP

SBASAB5 – MARCH 2024

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