CS47L35 datasheet(147/300 Pages) CIRRUS

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DS1085F3

147

CS47L35

4.11 Output Signal Path

When the OUT5L or OUT5R output signal path is enabled, the PDM interface clock signal is output on the SPKCLK pin.

The output signal paths support normal and high performance operating modes, as described in Section 4.11.3. The

SPKCLK frequency is set according to the operating mode of the relevant output path, as described in Table 4-72. The

OUT5_OSR bit is defined in Table 4-66.

Note that the SPKCLK frequencies noted in Table 4-72 assume that the SYSCLK frequency is a multiple of 6.144 MHz

(SYSCLK_FRAC = 0). If the SYSCLK frequency is a multiple of 5.6448 MHz (SYSCLK_FRAC=1), the SPKCLK frequency

is scaled accordingly.

The PDM output channels can be independently muted. When muted, the default output on each channel is a

DSD-compliant silent stream (0110_1001b). The mute output code can be programmed to other values if required, using

the SPK1_MUTE_SEQ field. The mute output code can be transmitted MSB-first or LSB-first; this is selectable using the

SPK1_MUTE_ENDIAN bit.

Note that the PDM Mute function is not a soft-mute; the audio output is interrupted immediately when the PDM mute is

asserted. It is recommended to use the output signal path mute function before applying the PDM mute. See Table 4-67

for details of the OUT5L_MUTE and OUT5R_MUTE bits.

The PDM output interface registers are described in Table 4-73.

The digital speaker (PDM) outputs SPKDAT and SPKCLK are intended for direct connection to a compatible external

speaker driver. A typical configuration is shown in Fig. 4-54.

Table 4-72. SPKCLK Frequency

OUT5_OSR

Description

SPKCLK Frequency

Normal mode

3.072 MHz

High Performance mode

6.144 MHz

Table 4-73. Digital Speaker (PDM) Output Control

Label

Default

Description

R1168 (0x0490)

PDM_SPK1_

CTRL_1

13 SPK1R_MUTE

PDM Speaker Output 1 (Right) Mute

0 = Audio output (OUT5R)

1 = Mute Sequence output

12 SPK1L_MUTE

PDM Speaker Output 1 (Left) Mute

0 = Audio output (OUT5L)

1 = Mute Sequence output

8SPK1_MUTE_

ENDIAN

PDM Speaker Output 1 Mute Sequence Control

0 = Mute sequence is LSB first

1 = Mute sequence output is MSB first

7:0 SPK1_MUTE_

SEQ[7:0]

0x69 PDM Speaker Output 1 Mute Sequence

Defines the 8-bit code that is output on SPKDAT (left) or SPKDAT (right) when muted.

R1169 (0x0491)

PDM_SPK1_

CTRL_2

0 SPK1_FMT

PDM Speaker Output 1 timing format

0 = Mode A (PDM data is valid at the rising/falling edges of SPKCLK)

1 = Mode B (PDM data is valid during the high/low phase of SPKCLK)

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