CS47L35 datasheet(151/300 Pages) CIRRUS

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DS1085F3

151

CS47L35

4.12 External Accessory Detection

4.12.2.1 MICDET Clamp Control

The MICDET clamp function can be configured using the MICD_CLAMP_MODE field; the selectable logic conditions

(derived from the JD1 and/or JD2 signals; see Table 4-74) provide support for different jack detect circuit configurations.

The MICD_CLAMP_OVD bit, when set, activates the MICDET clamp, regardless of other conditions.

Note: The MICD_CLAMP_OVD bit is enabled by default; the MICDET clamp is always active following power-on reset,

hardware reset, or software reset.

The MICDET clamp functionality (including the external IRQ) is maintained in Sleep Mode (see Section 4.13). This enables

a jack insertion event to be used to trigger a wake-up of the CS47L35. A summary of the jack detect and MICDET clamp

functionality, and their recommended usage in typical applications, is described in Section 4.12.2.5.

When the MICDET clamp is active, the MICDET1/HPOUTFB2 and HPOUTFB1/MICDET2 pins are short-circuited

together. The grounding of the MICDET pin is achieved via the applicable HPOUTFB pin; note that it is assumed that the

HPOUTFB connection is grounded externally, as shown in Fig. 4-57.

The configurable logic provides flexibility in selecting the appropriate conditions for activating the MICDET clamp. The

clamp status can be read using the MICD_CLAMP_STSx bits. Note that the MICD_CLAMP_STS1 and MICD_CLAMP_

STS2 bits provide the same information.

The MICDET clamp debounce is selected by setting MICD_CLAMP_DB, as described in Table 4-75. Note that, under

normal operating conditions, the debounce circuit uses the 32-kHz clock, which must be enabled whenever input

debounce functions are required. Input debounce is not provided in Sleep Mode; the MICD_CLAMP_DB bit has no effect

in Sleep Mode.

The MICDET clamp function is shown in Fig. 4-57. Note that the jack plug is shown partially removed, with the MICDET1

pin in contact with the headphone load.

Figure 4-57. MICDET Clamp Circuit

4.12.2.2 Interrupts and Write-Sequencer Control

An interrupt request (IRQ) event is generated whenever the MICDET clamp is asserted or deasserted; see Section 4.15.

Separate mask bits are provided to enable IRQ events on the rising and/or falling edge of the MICDET clamp status.

HPOUTFB/

MICDET2

MICDET1/

HPOUTFB2

MICBIASnx

* IN1BLP, IN1BRP

2.2 k

(±2%)

* Note: The Jack plug is shown

partially removed, with the MICDET1

pin in contact with the headphone load.

* see note

MICDET

Clamp Control

MICD_CLAMP_OVD

MICD_CLAMP_MODE

MICD_CLAMP_STSx

MICD_CLAMP_DB

When the MICDET Clamp is active in the configuration

shown, the MICDET1 pin is grounded via the

headphone jack ground connection.

* Note that the IN1Bxx analog mic

channels are recommended with the

external accessory detect function

CS47L35

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