CS43131 datasheet(31/156 Pages) CIRRUS

31 / 156 page

DS1155F1

CS43131

4.2 Analog Outputs

The CS43131 provides an analog output that is derived from the digital audio input ports. This section describes the

general flow of the analog outputs.

4.2.1

Analog Output Signal Flow

The CS43131 signal flow is shown in Fig. 4-1.

Figure 4-1. Analog Output Signal Flow

The CS43131 has 4 settings of full scale voltage, which are determined by OUT_FS[1:0]. When OUT_FS[1:0] = 11 and

HV_EN = 1, the +1dB_EN bit can boost the output voltage to 2 Vrms. In any other setting combination of OUT_FS[1:0] and

HV_EN, the +1dB_EN bit is ignored. The proper full scale voltage must be set first, and the digital volume settings is used

to control signal levels.

The CS43131 digital volume control allows independent control of the signal level in 1/2 dB increments from 0 dB

(0b0000 0000) to –127 dB (0b1111 1110) by using x_VOLUME_y (where "x" is either PCM or DSD; "y" is either A or B)

volume changes are implemented as dictated by PCM_SZC[1:0] and DSD_SZC in the signal control register (see

Section 7.4.3 and Section 7.5.5). If soft ramping is enabled, gain and attenuation changes are carried out by incrementally

changing the volume level in 1/8-dB steps, from the previous level to the new level. For PCM, when PCM_SZC[1:0] = 2,

the volume level changes at an approximate rate of 1 dB/ms. The volume level also changes at a rate of 1 dB/ms for DSD.

Both channels can be inverted independently by setting the INV_A and INV_B bits. Both channels can be swapped by

setting the x_SWAP_CHAN bit. Channel A content can be copied to channel B by setting the x_COPY_CHAN bit. Mono

mode can be enabled with proper setting of these bits.

The CS43131 provides individual ramp-up and ramp-down control options (from the global soft ramp settings) for two

specific scenarios. The PCM_RAMP_DOWN bit is for the scenario when the interpolation filter configuration switches (as

configured by the PCM Filter Option register) during PCM playback. DSD_RAMP_UP bit is for the scenario when DSD

playback recovers from detected DSD stream errors. Refer to each individual register description for setting details.

The CS43131 can mute both channels simultaneously or independently. Also, it can auto-mute on both PCM stream and

DSD stream when mute pattern is identified (defined in PCM_AMUTE and DSD_AMUTE). Additional signal and mute

control options can be found in Section 7.4.3 and Section 7.5.5.

Multibit



Modulator

Multibit



Modulator

Interpolation

Filter &

Volume

Control

Interpolation

Filter &

Volume

Control

DAC and

Filter

DAC and

Filter

–

HPINB

HPINA

HPOUTA

HPOUTB

DSD

Processor

DoP to

DSD

Engine

Audio

Source

HPREFB

HPREFA

DoP

DSD



HP_IN_EN p. 127

HP_IN_LP p. 127

HP_IN_EN p. 127

HP_IN_LP p. 127

PDN_HP

DSD_EN p. 126

MIX_PCM_PREP p. 126

MIX_PCM_DSD p. 126

PCM_SZC p. 129

PCM_RAMP_DOWN p. 129

PCM_VOLUME_B p. 128

PCM_VOLUME_A p. 128

PCM_INV_A p. 129

PCM_INV_B p. 129

PCM_SWAP_CHAN p. 129

PCM_COPY_CHAN p. 129

PCM_VOL_BEQA p. 129

PCM_AMUTE p. 129

PCM_AMUTEBEQA p. 129

PCM_MUTE_A p. 129

PCM_MUTE_B p. 129

FILTER_SLOW_FASTB

p. 128

PHCOMP_LOWLATB p. 128

HIGH_PASS p. 128

DEEMP_ON p. 128

NOS p. 128

DAC_OVFL_INT

p. 134

DSD_PRC_SRC p. 126

DSD_SPEED p. 126

STA_DSD_DET p. 126

INV_DSD_DET p. 126

DSD_VOLUME_B p. 124

DSD_VOLUME_A p. 125

DSD_INV_A p. 127

DSD_INV_B p. 127

DSD_VOL_BEQA p. 125

DSD_AMUTE p. 125

DSD_MUTE_A p. 125

+1dB_EN p. 127

OUT_FS p. 127

PCM_WBF_EN p. 128

PDN_HP

DSD_MUTE_B p. 125

DSD_ZERODB p. 126

DSD_HPF_EN p. 127

OUT_FS p. 127

DSD_SZC p. 125

DSD_RAMP_UP p. 125

DSD_SWAP_CHAN p. 127

DSD_COPY_CHAN p. 127

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