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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS43131 датащи(PDF) 14 Page - Cirrus Logic |
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CS43131 датащи(HTML) 14 Page - Cirrus Logic |
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14 / 156 page  14 DS1155F1 CS43131 3 Characteristics and Specifications HPOUTx RL = 600 CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 0, unless otherwise specified Dynamic range (defined in Table 3-1) 24-bit, 32-bit, DSD 16-bit A-weighted Unweighted A-weighted Unweighted 124 121 91 88 130 127 97 94 — — — — dB dB dB dB THD+N (defined in Table 3-1) 24-bit, 32-bit 16-bit DSD 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB 0 dB –20 dB –60 dB — — — — — — — — — –115 –97 –67 –94 –74 –34 –108 –97 –67 –109 — –61 –88 — –28 –101 — –61 dB dB dB dB dB dB dB dB dB Idle channel noise (A-weighted) (defined in Table 3-1) 24-bit, 32-bit, DSD — 0.55 — µV Full-scale output voltage 4.66 4.90 5.14 Vpp Output power — 5 — mW Interchannel isolation (defined in Table 3-1) 217 Hz 1 kHz 20 kHz — — — 120 120 100 — — — dB dB dB HPOUTx RL = 600 CL = 200 pF OUT_FS = 11 Volume = 0 dB +1dB_EN = 1, unless otherwise specified THD+N (defined in Table 3-1) 24-bit, 32-bit, DSD 0 dB — –105 — dB Full-scale output voltage 5.42 5.70 5.99 Vpp Output power — 6.8 — mW Other characteristics for HPOUTx Interchannel gain mismatch (defined in Table 3-1)— ±0.1 — dB Interchannel phase mismatch (defined in Table 3-1) — — ±0.01 ° Output offset voltage: Mute (defined in Table 3-1) — ±50 ±100 µV Gain drift (defined in Table 3-1) — ±100 — ppm/°C Load resistance (RL)600 — — Load capacitance (CL)— — 1 nF Turn-on time (defined in Table 3-1)— — 12 ms Click/pop during PDN_HP enable or disable A-weighted — ±50 ±100 µV 1.This table also applies to external VCP_FILT supply mode: CS43131 power up procedure is per description in Section 5.13.1; EXT_VCPFILT = 1; VCP_FILT+ and VCP_FILT– comply to Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN must be set to 1. 2.One LSB of triangular PDF dither is added to PCM data. 3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table. 4.DSD performance may be limited by the source recording. 0 dB-SACD = 50% modulation index. 5.The volume must be configured as indicated to achieve specified output characteristics. Table 3-4. Analog Output Characteristics (HV_EN = 1) 1 (Cont.) Test conditions (unless otherwise specified): Fig. 2-1 shows CS43131 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; HV_EN = 1; ASP_M/Sb = 1; typical, min/max performance data taken with VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–20 kHz; ASP_SPRATE = 0001 (LRCK = 44.1-kHz mode); PDN_XTAL = 0, MCLK_INT = 1, PLUS_1DB = 0, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing in DSD processor mode, DSD_ZERODB = 1 ; when testing noise related specifications (dynamic range, THD+N, idle channel noise), no external impedance on HPREFx. PCM and DSD Processor Mode Parameter 2,3,4 Minimum Typical Maximum Units |
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