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CS43131 датащи(PDF) 51 Page - Cirrus Logic

номер детали CS43131
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 датащи(HTML) 51 Page - Cirrus Logic

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DS1155F1
51
CS43131
4.9 Audio Serial Port (ASP)
Fig. 4-24 shows how LRCK frame start delay (xSP_FSD) controls the number of SCLK periods delay from the LRCK
synchronization edge to the start of frame data.
Figure 4-24. LRCK FSD and SCLK Polarity Example Diagram
Table 4-6. Serial Port Clock Generation—Supported Configurations for 32 bits and 2 Channels
Frequency (MHz)
LRCK/FSYNC
Rate (kHz)
SCLKs per LRCK Frame
xSP_N[15:0] xSP_M[15:0]
xSP_LCPR + 1 xSP_LCPR[10:0]
22.5792
32.000
64
63
40
441
44.100
64
63
1
8
48.000
64
63
20
147
88.200
64
63
1
4
96.000
64
63
40
147
176.400
64
63
1
2
192.000
64
63
80
147
352.800
64
63
1
1
24.576
32.000
64
63
1
12
44.100
64
63
147
1280
48.000
64
63
1
8
88.200
64
63
147
640
96.000
64
63
1
4
176.400
64
63
147
320
192.000
64
63
1
2
352.800
64
63
147
160
384.000
64
63
1
1
LRCK
01
Channel location (xSP_RX_CHn) = 0
FSD = 000
FSD = 001
FSD = 010
N-1
N-2
N-3
N-4
N-5
FSD = 011
0
FSD = 100
0.5
1
1.5
2
2.5
FSD = 101
End of frame
2
...
...
...
...
...
...
...
34567
89
...
...
01
Channel location (xSP_RX_CHn) = 0
N-1
N-2
N-3
N-4
N-5
End of frame
2
...
34567
89
...
01
Channel location (xSP_RX_CHn) = 0
N-1
N-2
N-3
N-4
N-5
End of frame
2
...
34567
89
01
Channel location (xSP_RX_CHn) = 0
N-1
N-2
N-3
N-4
N-5
End of frame
2
...
34567
89
...
SCLK
SDIN
SDIN
SCLK
SDIN
SCLK
SCLK
SDIN
SCPOL _IN = 0
SCPOL_OUT = 0
SCPOL _IN = 1
SCPOL_OUT = 0
SCPOL _IN = 0
SCPOL_OUT = 1
SCPOL _IN = 1
SCPOL_OUT = 1



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