CS43131 datasheet(25/156 Pages) CIRRUS

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DS1155F1

CS43131

3 Characteristics and Specifications

Slave

Mode

FSYNC setup time before SCLK latching edge 6

tSU:FSYNC

—

FSYNC hold time after SCLK latching edge 6

tH:FSYNC

5—

—

SCLK frequency

fSCLK

——

24.58

MHz

SCLK high period

tHI:SCLK

—

SCLK low period

tLO:SCLK

—

SDIN setup time before SCLK latching edge 8

tSU:SDI

—

SDIN hold time after SCLK latching edge 6

tH:SDI

5—

—

1.Output clock frequencies follow the internal master clock (MCLK_INT) frequency proportionally. Any deviation of the clock source from the nominal

supported rates are directly imparted to the output clock rate by the same factor (e.g., +100-ppm offset in the frequency of MCLK_INT becomes a

+100-ppm offset in LRCK/FSYNC and SCLK).

2.I2S interface timing

3.TDM interface timing

(shown with xSP_FSD = 010, xSP_LCHI = 1)

4.Applies to Master and Slave Modes, unless specified otherwise.

5.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to

768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.

6.Data may be latched/launched on either the rising or falling edge of SCLK.

7.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLK_INT period.

8.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the

SCLK launching specs in Table 3-20.

Table 3-21. DSD Switching Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds

(see Table 3-13).

Parameter 1,2

Symbol

Minimum Typical

Maximum

Units

DSDCLK duty cycle

—

DSDCLK pulse width low

tSCLKL

—

DSDCLK pulse width high

tSCLKH

—

DSDCLK frequency

(64× oversampled)

(128× oversampled)

(256x oversampled)

—1.024

2.048

4.096

2.8224

5.6448

11.2897

fMCLK_INT/8

fMCLK_INT/4

fMCLK_INT/2

MHz

DSDA/DSDB valid to DSDCLK rising setup time

tSDLRS

—

DSDCLK rising to DSDA or DSDB hold time

tSDH

—

DSD clock to data transition (Phase Modulation Mode)

(64× oversampled)

(128× oversampled)

tDPM

–20

–10

—

Table 3-20. Serial-Port Interface Characteristics (Cont.)

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds

(see Table 3-13).

Parameters 1,2,3,4

Symbol

Minimum

Typical

Maximum

Units

SCLK

(CPOL = 1)

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK–FSYNC

1/Fs

...

fSCLK = N · Fs

tSU:FSYNC

tH:FSYNC

tLO:SCLK

tHI:SCLK

SCLK

(CPOL = 0)

...

1/fSCLK

...

SCLK

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK-FSYNC

1/fSCLK

Don’t Care

Frame location 0

Frame location N -1

1/Fs

...

fSCLK = N · Fs

tSU :FSYNC

tH:FSYNC

tHI:FSYNC

tLO:SCLK

tHI:SCLK

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