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CS43131 датащи(PDF) 43 Page - Cirrus Logic

номер детали CS43131
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 датащи(HTML) 43 Page - Cirrus Logic

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DS1155F1
43
CS43131
4.6 Clocking Architecture
When the PLL reference clock is supplied to the device through the XTI/MCLK pin, it must comply with the phase-noise
mask shown in Fig. 4-15.
Figure 4-15. MCLK Phase Noise Mask With PLL
Further restrictions are listed in Table 4-3.
Table 4-3. MCLK Source Restrictions
Internal
MCLK
Source
MCLK_SRC_SEL MCLK_INT
Restrictions
Direct MCLK
or XTAL
00
0
• Nominal MCLK_INT frequency = 24.576 MHz
• All specified CLKOUT frequencies (generated by PLL or XTAL) are supported
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally
1
• Nominal MCLK_INT frequency = 22.5792 MHz
• All specified CLKOUT frequencies (generated by PLL or XTAL) are supported
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally
PLL
01
0
• Nominal MCLK_INT frequency = 24.576 MHz
• PDN_PLL = 0 and PLL properly configured to generate 24.576 MHz given reference input
frequency on XTI/MCLK pin
• Only MCLK_INT on CLKOUT is supported on CLKOUT pin
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally
1
• Nominal MCLK_INT frequency = 22.5792MHz
• PDN_PLL = 0 and PLL properly configured to generate 22.5792 MHz given reference input
frequency on XTI/MCLK pin
• Only MCLK_INT on CLKOUT is supported on CLKOUT pin
• CLKOUT outputs (/2, /3, /4, /8 divide) optionally
RCO
10
X
• No MCLK_INT selection necessary. DAC playback is not supported. I2C port and HPIN_x
pins are supported.



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