CS43131 datasheet(44/156 Pages) CIRRUS

44 / 156 page

DS1155F1

CS43131

4.7 Clock Output and Fractional-N PLL

Figure 4-16. MCLK Source Switching

A source to MCLK_INT, either the XTAL (or external MCLK), PLL, or the RCO, must be provided as long as CS43131 is

operating; otherwise, the CS43131 will enter a non-responsive state. The only way to recover from this non-responsive

state is either through a reset or POR event. Switching MCLK sources during DAC operation causes audible artifacts, but

does not put the device in an unrecoverable state. In an MCLK source-switching event, the destined clock source must be

present and ready before switching occurs.

After POR or reset event, RCO is selected as default source of MCLK_INT.

4.6.1.1 Internal RC Oscillator

As described in Section 4.6.1, the CS43131 includes an internal RC oscillator that can be used as a clock source for

peripheral circuit such as control port or charge pump.

4.7 Clock Output and Fractional-N PLL

The CS43131 clock output can be used as a master clock for other data-conversion or signal-processing components,

which requires synchronous timing to the CS43131.

The CLKOUT output is enabled by clearing PDN_CLKOUT.

Figure 4-17. CLKOUT Source Selection

Once enabled, CLKOUT is generated either from the internal crystal oscillator output (when used) or from the integrated

fractional-N PLL; it can be selected by CLKOUT_SEL. CLKOUT_DIV can be used to set /2, /3, /4, or /8 to divide the

selected clock source to targeted frequency.

4.7.1

Fractional-N PLL

The CS43131 has an integrated fractional-N PLL to support the clocking requirements of various applications. This PLL

can be enabled or disabled by clearing or setting PDN_PLL bit. The input reference clock for the PLL is signal on XTI/

MCLK pin (crystal-generated or external-feed).

Internal

PLL

XTI/MCLK

Internal MCLK

CLKOUT

RCO

CLKOUT_SEL p. 118

PDN_PLL p. 115

MCLK_SRC_SEL

CLKOUT_DIV p. 118

MCLK_INT p. 114

XTI/MCLK

PLL_OUT

CLKOUT

CLKOUT_DIV

CLKOUT_SEL p. 118

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