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CS43131 датащи(PDF) 23 Page - Cirrus Logic

номер детали CS43131
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 датащи(HTML) 23 Page - Cirrus Logic

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DS1155F1
23
CS43131
3 Characteristics and Specifications
PLL reference clock input
11.2896
22.5792
12.2880
24.5760
9.6000
19.2000
12.0000
24.0000
13.0000
26.000
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL reference clock input jitter
50
ps
Table 3-16. Crystal Characteristics
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; TA = +25°C
Parameters 1
1.Refer to Section 5.3 for supported crystal options.
Symbol
Minimum
Typical
Maximum
Units
Crystal oscillator frequency
fXTAL
22.57
22.5792/ 24.576
24.58
MHz
Crystal load capacitance
CL_XTAL
5—
8
pF
Equivalent series resistance
esrXTAL
——
100
Startup time
tXTAL_pup
——
6.5
ms
Shunt capacitance
CO
——
0.8
pF
Maximum drive level
200
µW
Table 3-17. Power-Supply Rejection Ratio (PSRR) Characteristics
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; input test signal held low (all zero data); GNDA = GNDL = GNDCP
= 0 V; voltages are with respect to ground; VL = VA = VD = 1.8 V, VP = 3.6 V; When testing PSRR, PCM input test signal held low (all zero data); TA =
+25°C; PCM_AMUTE = 0.
Parameter 1
1.PSRR test configuration: Typical PSRR can vary by approximately 6 dB below
the indicated values.
Minimum Typical
Maximum
Units
HPOUTx
PSRR with 100-mVpp signal AC coupled to VA supply
PDN_HP = 0, HP_IN_EN = 0
217 Hz
1 kHz
20 kHz
75
75
70
dB
dB
dB
HPOUTx
PSRR with 100-mVpp signal AC coupled to VCP supply
PDN_HP = 0, HP_IN_EN = 0
217 Hz
1 kHz
20 kHz
80
80
60
dB
dB
dB
HPOUTx
PSRR with 100-mVpp signal AC coupled to VP supply
PDN_HP = 0, HP_IN_EN = 0
217 Hz
1 kHz
20 kHz
100
100
80
dB
dB
dB
HPOUTx (0-dB analog gain)
PSRR with 100-mVpp signal AC coupled to VCP supply
PDN_HP = 1, HP_IN_EN = 1, RL = 32 
217 Hz
1 kHz
20 kHz
80
80
60
dB
dB
dB
HPOUTx (0-dB analog gain)
PSRR with 100-mVpp signal AC coupled to VP supply
PDN_HP = 1, HP_IN_EN = 1, RL = 32 
217 Hz
1 kHz
20 kHz
100
100
80
dB
dB
dB
Table 3-15. PLL Characteristics (Cont.)
Test conditions (unless specified otherwise): GNDD = GNDCP = GNDA = 0 V; voltages are with respect to ground; VP = 3.6 V, VCP = VA = 1.8 V, VL =
VD = 1.8 V; PLL reference input must meet the phase-noise mask specified in Fig. 4-15; TA = +25°C.
Parameters
Symbol
Minimum
Typical Maximum Units
Operational Amplifier
OUT
GND
Power DAC
OUT
GND
PWR
DUT
+5 V
+5 V
+
+–
+
OUT
Analog Generator
Analog Analyzer
Analog Test Equipment
Analog Output PSRR



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