CS43131 datasheet(24/156 Pages) CIRRUS

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DS1155F1

CS43131

3 Characteristics and Specifications

Table 3-18. DC Characteristics

Test conditions (unless otherwise specified): Fig. 2-1 shows CS43131 connections; GNDD = GNDA = GNDCP = 0 V; all voltages with respect to ground.

Parameters

Minimum

Typical

Maximum Units

VCP_FILT (No load connected to HPOUTx)

EXT_VCPFILT = 0

VP_LDO Mode

VCP_FILT+ pin (HV_EN = 1)

VCP_FILT+ pin (HV_EN = 0)

VCP_FILT– pin (HV_EN = 1)

VCP_FILT– pin (HV_EN = 0)

—

3.0

2.6

–3.0

–2.6

—

VCP Mode

VCP_FILT+ pin

VCP_FILT– pin

—

VCP

–VCP

—

–VA

–VA pin

—

– VA

—

Alternate headphone path

switch-on characteristics

PDN_HP = 1, HP_IN_EN = 1

On-resistance

—

0.4

—



rON matching between channels

—

0.05

—



Other DC characteristics

FILT+ voltage

—

–0.35

—

FILT– voltage

—

0.35

—

HP output current limiter on threshold.

—

120

160

VD power-on

reset threshold

(VPOR)

Down

—

1.15

0.950

—

Table 3-19. Power Consumption

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

performance data taken with VA = VCP = VD = VL = 1.8 V; VP = 3.6 V; TA = +25°C; ASP_SPRATE = 0001(44.1-kHz mode); MCLK_INT= 1

(22.5792 MHz); MCLK_SRC_SEL = 00; +1dB_EN = 1; all other fields are set to defaults; no signal on any input; control port inactive; all serial ports are

set to Slave or Master Mode as indicated, input clock/data are held low unless active; test load is RL = 32  and CL = 1 nF for HPOUTx; measured values

include currents consumed by the DAC and do not include current delivered to external loads unless specified otherwise (e.g., from HPOUTx outputs);

see Fig. 2-1.

Use Cases

Typical Current (µA)

Total

Power

(µW)

POUT

iVCP

iVA

iVD

iVL

iVP

1Off 1

1.Off configuration: Clock/data lines held low; RESET = LOW; VA = VD = VL = 0 V, VCP = 0 V, VP = 3.6 V.

—0

Standby 2

2.Standby configuration: Clock/data lines held low; RESET = HIGH; VA = VD = VL = 1.8 V, VCP = 1.8 V, VP = 3.6 V; HP_DETECT_CTRL = 11 (enabled);

HPDETECT_PLUG_INT_MASK=0 (unmasked); PDN_XTAL = 1, MCLK_SRC_SEL = 10 (RCO selected as MCLK source).

HPDETECT enabled

—

256

576

3 A Playback

External MCLK = 22.5792 MHz, I2S/DoP

Stereo HPOUT

Quiescent 3

3.Quiescent configuration: data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V. Serial port, I2S/DoP Mode (ASP and

SDIN, ASP_M/Sb = 0); PDN_XTAL = 1.

3808

7835

2786

26074

0.1mW

12363

7862

2004

40199

Alternate HP path stereo HPIN enabled 4

4.Quiescent configuration: PDN_XTAL = 1; MCLK_SRC_SEL = 10 (RCO selected as MCLK source); alternate headphone path (PDN_HP = 1, HPOUT_

CLAMP = 1, HP_IN_EN = 1, HP_IN_LP = 1); data lines held low; RESET = HIGH; VA = 1.8 V, VD = VL = VCP = 1.8 V, VP = 3.6 V.

Quiescent

186

625

Table 3-20. Serial-Port Interface Characteristics

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH thresholds

(see Table 3-13).

Parameters 1,2,3,4

Symbol

Minimum

Typical

Maximum

Units

FSYNC frame rate

(See

Section 4.9.5)

kHz

FSYNC high period 5

tHI:FSYNC

1/fSCLK

—

(n–1)/fSCLK

Master

Mode

FSYNC duty cycle

xSP_5050 = 1

—

FSYNC delay time after SCLK launching edge 6

tD:CLK–FSYNC

——10

SCLK frequency

fSCLK

——

fMCLK_INT

MHz

SCLK high period 7

tHI:SCLK

1/(2•fSCLK) –

1/fMCLK_INT

—1/(2•fSCLK) +

1/fMCLK_INT

SDIN setup time before SCLK latching edge 6

tSU:SDI

—

SDIN hold time after SCLK latching edge 6

tH:SDI

5—

—

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