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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CS43131 датащи(PDF) 96 Page - Cirrus Logic |
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CS43131 датащи(HTML) 96 Page - Cirrus Logic |
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96 / 156 page  96 DS1155F1 CS43131 5.13 Example Sequences 14 Configure XSP Clock XSP Clock Configuration. 0x40028 0x1C Reserved XSP_M/SB XSP_SCPOL_OUT XSP_SCPOL_IN XSP_LCPOL_OUT XSP_LCPOL_IN 000 1 1 1 0 0 Set XSP port to be Master Set output SCLK polarity Input SCLK polarity is don’t care Set Output LRCLK polarity Input LRCLK polarity is don’t care 15 Configure XSP Frame XSP Frame Configuration. 0x40029 0x0A Reserved XSP_STP XSP_5050 XSP_FSD 000 0 1 010 Configure XSP port to accept I2S input 16 Set XSP Channel Location XSP Channel 1 Location. 0x60000 0x00 XSP_RX_CH1 0x00 XSP Channel 1 starts on SCLK0 XSP Channel 2 Location. 0x60001 0x00 XSP_RX_CH2 0x00 XSP Channel 2 starts on SCLK0 17 Set XSP Channel Size and Enable XSP Channel 1 Size and Enable. 0x6000A 0x06 Reserved XSP_RX_CH1_AP XSP_RX_CH1_EN XSP_RX_CH1_RES 0000 0 1 10 XSP Channel 1 Active Phase XSP Channel 1 Enable XSP Channel 1 Size is 24 bits XSP Channel 2 Size and Enable. 0x6000B 0x0E Reserved XSP_RX_CH2_AP XSP_RX_CH2_EN XSP_RX_CH2_RES 0000 1 1 10 XSP Channel 2 Active Phase XSP Channel 2 Enable XSP Channel 2 Size is 24 bits 18 Configure DSD Processor 19 Configure DSD Volume DSD Volume A. 0x70001 0x00 DSD_VOLUME_A 0x00 Channel A volume set to 0 dB 20 Configure DSD path Signal Control 1 DSD Processor Path Signal Control 1. 0x70002 0xCC DSD_RAMP_UP DSD_VOL_BEQA DSD_SZC Reserved DSD_AMUTE DSD_AMUTE_BEQA DSD_MUTE_A DSD_MUTE_B 1 1 0 0 1 1 0 0 DSD Volume B equals DSD volume A Immediate change Mute occurs after 256 repeated 8-bit DSD mute patterns Mute happens only when mute pattern is detected in both channels Function is disabled Function is disabled 21 Configure DSD Interface DSD Interface Configuration. 0x70003 0x00 Reserved DSD_M/SB DSD_PM_EN DSD_PM_SEL 0000 0 0 0 0 DSD_M/SB is don’t care Function is disabled Function is disabled 22 Configure DSD path Signal Control 2 DSD Processor Path Signal Control 2. 0x70004 0x70 Reserved DSD_PRC_SRC DSD_EN Reserved DSD_SPEED STA_DSD_DET INV_DSD_DET 0 11 1 0 0 0 0 Set source of DSD processor to XSP Enable DSD playback Set DSD clock speed to 64 •FS Static DSD detection disabled Invalid DSD detection disabled 23 Configure DSD path Signal Control 3 DSD Processor Path Signal Control 3. 0x70006 0xC0 DSD_ZERODB DSD_HPF_EN Reserved SIGCTL_DSDEQPCM DSD_INV_A DSD_INV_B DSD_SWAP_CHAN DSD_COPY_CHAN 1 1 0 0 0 0 0 0 DSD stream volume setting Enable DSD HPF Function is disabled Function is disabled Function is disabled Function is disabled Function is disabled 24 Configure HP Output for 1.732 Vrms Example 5-18. DoP and PCM Mixing (Cont.) STEP TASK REGISTER/BIT FIELDS VALUE DESCRIPTION |
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