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CS43131 датащи(PDF) 18 Page - Cirrus Logic

номер детали CS43131
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 датащи(HTML) 18 Page - Cirrus Logic

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18
DS1155F1
CS43131
3 Characteristics and Specifications
HPOUTx;
RL = 32 
CL = 200 pF
OUT_FS = 01
Volume = 0 dB
HV_EN = 0,
unless otherwise
specified
Dynamic range
(defined in Table 3-1)
24-bit, 32-bit
A-weighted
117
123
dB
Dynamic range
(MCLK = 19.2 MHz,
MCLK_SRC_SEL = 01,
MCLK_INT = 1)
24-bit, 32-bit (DRE_EN = 1)
24-bit, 32-bit (DRE_EN = 0)
A-weighted
Unweighted
A-weighted
Unweighted
115
88
94
64
121
94
100
70
dB
dB
dB
dB
THD+N (20 Hz–20 kHz,
defined in Table 3-1)
24-bit, 32-bit
0 dB
–20 dB
–60 dB
–110
–92
–62
–104
–56
dB
dB
dB
THD+N (20 Hz–90 kHz,
defined in Table 3-1)
24-bit, 32-bit
0 dB
–20 dB
–60 dB
–89
–78
–38
–83
–32
dB
dB
dB
Idle channel noise
(A-weighted)
(defined in Table 3-1)
24-bit, 32-bit
0.69
µV
Full-scale output voltage
2.68
2.81
2.96
Vpp
Output power
30.8
mW
Interchannel isolation 4 (defined in Table 3-1)
217 Hz
1 kHz
20 kHz
110
105
90
dB
dB
dB
Other characteristics
for HPOUTx
Interchannel gain mismatch (defined in Table 3-1)—
±0.1
dB
Interchannel phase mismatch (defined in Table 3-1)
±0.01
°
Output offset voltage: Mute (defined in Table 3-1)
±50
±100
µV
Gain drift (defined in Table 3-1)
±100
ppm/°C
Load resistance (RL)6
Load capacitance (CL)—
1
nF
Turn-on time (defined in Table 3-1)—
12
ms
Click/pop during PDN_HP enable or disable
A-weighted
±50
±100
µV
1.This table also applies to external VCP_FILT supply mode: CS43131 power up procedure is per description in Section 5.13.1; EXT_VCPFILT = 1;
VCP_FILT+ and VCP_FILT– comply to
Table 3-2 when EXT_VCPFILT = 1; in this mode, HV_EN must be set to 1.
2.One LSB of triangular PDF dither is added to PCM data.
3.Referred to the typical full-scale voltage. Applies to all THD+N and dynamic range values in the table.
4.HP output test configuration. Symbolized component values are specified in the test
conditions.
Table 3-7. Headphone Load Measurement
Test conditions (unless specified otherwise): Fig. 2-1 shows CS43131 connections; GNDD = GNDCP = GNDA = 0 V; voltages are with respect to
ground; typical performance data taken with VP = 3.6 V, VCP = VA = 1.8 V, VL = VD = 1.8 V; min/max performance data taken with VP = 3.6 V,
VCP = VA = 1.8 V, VL = VD = 1.8 V; TA = +25°C. MCLK_INT = 1, PDN_XTAL = 0, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz)
Parameters
Symbol
Minimum
Typical Maximum Units
Frequency range
—20
20k
Hz
Frequency resolution
5.94
Hz
Table 3-6. Wideband Flatness Mode Analog Output Characteristics 1 (Cont.)
Test conditions (unless otherwise specified): Fig. 2-1 shows CS43131 connections; input test signal is a 32-bit, full-scale 997-Hz sine wave (unless
specified otherwise); GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground; ASP_M/Sb = 1; typical, min/max performance data taken with
VA = VCP = 1.8 V; VL = VD = 1.8 V; VP = 3.6 V; TA = +25°C; measurement bandwidth is 20 Hz–90 kHz; ASP_SPRATE = 0110 (LRCK = 192-kHz mode);
PDN_XTAL = 0, MCLK_INT = 1, and MCLK_SRC_SEL = 00 (crystal frequency fXTAL = 22.5792 MHz); Volume = 0 dB; when testing noise related
specifications (dynamic range, THD+N, idle channel noise), no external impedance on HPREFx.
Wideband Flatness Mode Parameter 2,3
Minimum
Typical
Maximum
Units
Test Load
HPOUTA
CLA
HPREFA
RLA
Measurement
Device
+
+
HPOUTB
HPREFB
CH1
CH2
CLB
RLB



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