CS43131 datasheet(6/156 Pages) CIRRUS

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DS1155F1

CS43131

1.3 Pin Descriptions

Table 1-1. Pin Descriptions

Pin Name

QFN

Pin #

WLCSP

Ball

Power

Supply

I/O

Pin Description

Internal

Connection

Digital I/O

Driver

Digital I/O

Receiver

ADR

I Address Bit (I²C). In I²C Mode, ADR is a chip address pin.

—

CLKOUT

O CLK Output. Single-ended clock output sourced from PLL or

buffered crystal.

Weak

pull-down

CMOS

output

—

SCLK1

I/O Serial Audio Input Bit Clock 1. Serial bit clock for audio data on

the SDIN pins.

Weak

pull-down

CMOS

output

Hysteresis

on CMOS

input

LRCK1

I/O Serial Audio Input Left/Right Clock. Word-rate clock for the

audio data on the SDIN pins.

Weak

pull-down

CMOS

output

Hysteresis

on CMOS

input

SDIN1

I Serial Audio Input Data Port. Audio data serial input pin 1.

Weak

pull-down

—

Hysteresis

on CMOS

input

DSDA/

SDIN2

I DSD Data Input A/Serial Data In 2. DSD audio or PCM audio

data serial input pin 2.

Weak

pull-down

—

Hysteresis

on CMOS

input

DSDB/

LRCK2

I/O DSD Data Input B/Serial Audio Input Left/Right Clock 2. DSD

audio data serial input pin or word rate clock for the audio data on

the SDIN2 pin.

Weak

pull-down

CMOS

output

Hysteresis

on CMOS

input

DSDCLK/

SCLK2

I/O DSD Clock Input/Serial Audio Input Bit Clock 2. DSD clock

input. Serial bit clock for audio data on the SDIN2 pin.

Weak

pull-down

CMOS

output

Hysteresis

on CMOS

input

INT

O Interrupt. When pulled up, works as system interrupt pin. Open

drain, active low programmable.

—CMOS

open-drain

output

—

RESET

I System Reset. The device enters system reset when enabled.

—

Hysteresis

on CMOS

input

SDA

I/O Serial Control Data I/O (I²C). In I²C Mode, SDA is the control I/O

data line.

—CMOS

open-drain

output

Hysteresis

on CMOS

input

SCL

I Software Clock (I²C). Serial control interface clock used to clock

control data bits into and out of the CS43131.

—

Hysteresis

on CMOS

input

XTI/MCLK

I Crystal/Oscillator Input/MCLK In. Crystal or digital clock input

for the master clock.

Weak

pull-down

—

Hysteresis

on CMOS

input

XTO

O Crystal/Oscillator Output. Crystal output.

Weak

pull-down

CMOS

output

—

FILT+

FILT–

O Positive/Negative Voltage Reference. Positive/negative

reference voltage for DAC.

——

—

HP_

DETECT

I Headphone Detect. Can be configured to be debounced on

unplugged and plugged events before it is presented as a

noninterrupt status bit (HPDETECT).

—Hi-Z

—

HPINB

HPINA

VCP_

FILT±

I Headphone Audio Input. For interfacing low power audio source,

an alternate analog input path for the headphone output. Refer to

analog specification table for full-scale input level.

Weak

pull-down

——

HPOUTB

HPOUTA

VCP_

FILT±

O Headphone Audio Output. Refer to analog specification table for

full-scale output level.

——

—

HPREFB

HPREFA

VCP_

FILT±

I Headphone Output Reference. Reference for headphone

amplifier and detect.

——

—

N/A

I Logic Power. Input/Output power supply, typically +1.8 V.

—

N/A

I Internal Digital Power. Internal digital power supply, typically

+1.8 V.

——

—

N/A

I Analog Power. Power supply for the internal analog section.

—

Digital I/O

Analog I/O

Power Supplies

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