CS43131 datasheet(59/156 Pages) CIRRUS

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DS1155F1

CS43131

4.13 Control Port Operation

The control port is used to access control registers and on-chip memory locations, allowing the device to be configured for

desired operational modes and formats. Control port operation may be completely asynchronous with respect to the audio

sample rates. However, to avoid potential interference problems, control port pins must remain static if no operation is

required.

The control port operates using a I2C interface with the CS43131 acting as a slave device. Device communication must

not begin until tPUD (refer to Table 3-22) after power conditions are ready and RESET is released.

4.13.1 I2C Control Port Operation

The I2C control port operates completely asynchronously with the audio sample rates. However, to avoid interference

problems, the I2C control-port pins must remain static if no operation is required.

The control-port uses the I2C interface, with the chip acting as a slave device. The I2C control port can operate in the

following modes:

• Standard Mode (SM), with a bit rate of up to 100 kbit/s

• Fast Mode (FM), with a bit rate of up to 400 kbit/s

• Fast Mode Plus (FM+), with a bit rate of up to 1 Mbit/s

SDA is a bidirectional data line. Data is clocked into and out of the CS43131 by the SCL clock. Fig. 4-32, Fig. 4-33, and

Fig. 4-34 show signal timings for read and write cycles. A Start condition is defined as a falling transition of SDA while SCL

is high. A stop condition is defined as a rising transition of SDA while SCL is high. All other transitions of SDA must occur

while SCL is low. Note that when HP_IN_LP is set, only SM and FM modes are supported.

To configure the last two bits of I2C address, CS43131 detects the ADR resistor connection type and measures the

resistance upon a device power up (POR event) or after a hardware reset event (RESET deasserted). Based on the

detected resistance, the I2C address is latched and cannot be changed until the next hardware reset event. The I2C

address configuration is not ready until tPUD after the hardware reset event. During this period, the CS43131 does not

respond to any user-issued I2C command. After configuration, the IC tristates the ADR pin and becomes high impedance

internally to avoid a constant bias current.

To directly connect the ADR pin and ground, the last two bits of the I2C address are configured as the default 00. For the

other options, use a resistor (with 5% accuracy) as suggested in the Table 4-12.

If the operation is a write, the 3 bytes after the chip address are the memory address pointer (MAP) that select the address

of the register to be read or written to next. The byte following the MAP is the control byte. Bit[0] of the control byte, INCR,

selects whether autoincrementing is to be used (INCR = 1), allowing successive reads or writes of consecutive registers.

Bits[2:1] of the control byte indicate the size of the data for the autoincrement to be acted on. Table 4-13 explains the

format for the I2C control byte.

Table 4-12. I2C Address Configurations

Connection Type

Resistor Value (

)

Last Two Bits of I2C Address

Pull-up to VL

4990

Pull-down to GND

4990

Pull-down to GND

00 (Default)

Table 4-13. I2C Control-Byte Format

Bit

Name

Description

7:3

—

Reserved

Default: 0

2:1

SIZE

00 8-bit (1 byte)

01–11 Reserved

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