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CS43131 датащи(PDF) 116 Page - Cirrus Logic

номер детали CS43131
подробное описание детали  130-dB, 32-Bit High-Performance DAC with Integrated Headphone Driver and Impedance Detection
PDF  156 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43131 датащи(HTML) 116 Page - Cirrus Logic

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DS1155F1
CS43131
7.2 PLL Registers
7.2 PLL Registers
7.2.1
PLL Setting 1
Address 0x30001
R/W
76543210
—
PLL_START
Default
00000000
Bits
Name
Description
7:1
—
Reserved
0
PLL_START PLL start bit. Enable PLL output after it has been properly configured.
0 (Default) PLL is not started
1 PLL is started
7.2.2
PLL Setting 2
Address 0x30002
R/W
76543210
PLL_DIV_FRAC_0
Default
00000000
Bits
Name
Description
7:0
PLL_DIV_
FRAC_0
PLL fractional portion of divide ratio LSB. There are 3 bytes of PLL feedback divider fraction portion and this is LSB byte;
e.g., 0xFF means (2-17 + 2-18 + …+2-24).
0000 0000 (Default)
7.2.3
PLL Setting 3
Address 0x30003
R/W
76543210
PLL_DIV_FRAC_1
Default
00000000
Bits
Name
Description
7:0
PLL_DIV_
FRAC_1
PLL fractional portion of divide ratio middle byte; e.g., 0xFF means (2-9 + 2-10 + …+2-16).
0000 0000 (Default)
7.2.4
PLL Setting 4
Address 0x30004
R/W
76543210
PLL_DIV_FRAC_2
Default
00000000
Bits
Name
Description
7:0
PLL_DIV_
FRAC_2
PLL fractional portion of divide ratio MSB; e.g., 0xFF means (2-1 + 2-2 + …+2-8).
0000 0000 (Default)
7.2.5
PLL Setting 5
Address 0x30005
R/W
76543210
PLL_DIV_INT
Default
01000000
Bits
Name
Description
7:0 PLL_DIV_INT PLL integer portion of divide ratio. Integer portion of PLL feedback divider.
0100 0000 (Default)



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