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CS43131 датащи(PDF) 106 Page - Cirrus Logic |
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CS43131 датащи(HTML) 106 Page - Cirrus Logic |
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106 / 156 page ![]() 106 DS1155F1 CS43131 6 Register Quick Reference 6 Register Quick Reference The registers for each CS43131 module are located at specific base addresses within the 24-bit register address space. The organization of this register space is summarized in Table 6-1. Notes: Default values are shown below the bit field names. The default values in all reserved bits must be preserved. 6.1 Global Registers 6.2 PLL Registers Table 6-1. Register Base Addresses Base Address Module Reference 0x01 0000 Global Registers Section 6.1 0x03 0000 PLL Registers Section 6.2 0x04 0000 ASP and XSP Registers Section 6.3 0x06 0000 DSD Registers Section 6.4 0x08 0000 Headphone and PCM Registers Section 6.5 0x0F 0000 Interrupt Status and Mask Registers Section 6.6 Address Function 7 654321 0 0x01 0000 Device ID A and B (Read Only) DEVIDA DEVIDB p. 113 0 100001 1 0x01 0001 Device ID C and D (Read Only) DEVIDC DEVIDD p. 113 0 001001 1 0x01 0002 Device ID E (Read Only) DEVIDE — p. 113 0 001000 0 0x01 0004 Revision ID (Read Only) AREVID MTLREVID p. 113 xxx xxxxx 0x01 0005 Subrevision ID (Read Only) SUBREVID p. 113 0 x x x x x x x 0x01 0006 System Clocking Control — MCLK_INT MCLK_SRC_SEL p. 114 0 000011 0 0x01 0007– 0x01 000A Reserved — 0 000000 0 0x01 000B Serial Port Sample Rate —ASP_SPRATE p. 114 0 000000 1 0x01 000C Serial Port Sample Bit Size — XSP_SPSIZE ASP_SPSIZE p. 114 0 000010 1 0x01 000D Pad Interface Configuration — XSP_3ST ASP_3ST p. 114 0 000001 1 0x01 000E– 0x01 FFFF Reserved — 0 000000 0 0x02 0000 Power Down Control PDN_XSP PDN_ASP PDN_DSDIF PDN_HP PDN_XTAL PDN_PLL PDN_CLKOUT — p. 115 1 111111 0 0x02 0001– 0x02 0051 Reserved — 0 000000 0 0x02 0052 Crystal Setting — XTAL_IBIAS p. 115 00 0 0 0 1 0 0 0x02 0053– 0x03 0000 Reserved — 0 000000 0 Address Function 7 654321 0 0x03 0001 PLL Setting 1 — PLL_START p. 116 0 000000 0 0x03 0002 PLL Setting 2 PLL_DIV_FRAC_0 p. 116 0 000000 0 0x03 0003 PLL Setting 3 PLL_DIV_FRAC_1 p. 116 0 000000 0 0x03 0004 PLL Setting 4 PLL_DIV_FRAC_2 p. 116 0 000000 0 |
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