P5021 datasheet(131/155 Pages) NXP

131 / 155 page

Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

131

3.1.2

Platform to SYSCLK PLL ratio

The allowed platform clock to SYSCLK ratios are shown in this table.

Note that in synchronous DDR mode, the DDR data rate is the determining factor for selecting the platform bus frequency

because the platform frequency must equal the DDR data rate.

In asynchronous DDR mode, the memory bus clock frequency is decoupled from the platform bus frequency.

3.1.3

e5500-64 core complex/ FMan to SYSCLK PLL ratio

The clock ratio between SYSCLK and each of the two core complex PLLs and FMan PLL is determined at power up by the

binary value of the RCW field CCn_PLL_RAT. (Note: n=1 or 2 are the core complex PLLs, n=3 is the FMan PLL). This table

describes the supported ratios. Note that a core complex/ FMan PLL setting targeting 1 GHz and above must set RCW field

CCn_PLL_CFG = 0b10, for setting targeting below 1 GHz CCn_PLL_CFG=0b00.

This table lists the supported core complex/ FMan to SYSCLK ratios.

Table 95. Platform to SYSCLK PLL ratios

Binary value of

SYS_PLL_RAT

Platform:SYSCLK ratio

0_0101

5:1

0_0110

6:1

0_0111

7:1

0_1000

8:1

All Others

Reserved

Table 96. Core complex/ FMan PLL to SYSCLK ratios

Binary value of

CCn_PLL_RAT

Core cluster:SYSCLK ratio

0_1000

8:1

0_1001

9:1

0_1010

10:1

0_1011

11:1

0_1100

12:1

0_1110

14:1

0_1111

15:1

1_0000

16:1

1_0001

17:1

1_0010

18:1

1_0100

20:1

1_0110

22:1

All Others

Reserved

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