P5021 datasheet(129/155 Pages) NXP

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Hardware design considerations

P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Freescale Semiconductor

129

The sinusoidal jitter in the total jitter tolerance may have any amplitude and frequency in the unshaded region of Figure 44.

Hardware design considerations

3.1

System clocking

This section describes the PLL configuration of the chip.

This device includes nine PLLs, as follows:

•

There are two selectable core cluster PLLs which generate a core clock from the externally supplied SYSCLK input.

Core complex 0–1 can select from either CC1 PLL or CC2 PLL. The frequency ratio between the core cluster PLLs

and SYSCLK is selected using the configuration bits as described in Section 3.1.3, “e5500-64 core complex/ FMan to

SYSCLK PLL ratio.” The frequency for each core complex 0–1 is selected using the configuration bits as described

in Table 97.

•

The platform PLL generates the platform clock from the externally supplied SYSCLK input. The frequency ratio

between the platform and SYSCLK is selected using the platform PLL ratio configuration bits as described in

Section 3.1.2, “Platform to SYSCLK PLL ratio.”

•

The DDR block PLL generates the DDR clock from the externally supplied SYSCLK input (asynchronous mode) or

from the platform clock (synchronous mode). The frequency ratio is selected using the Memory Controller Complex

PLL multiplier/ratio configuration bits as described in Section 3.1.5, “DDR controller PLL ratios.”

•

The FMan PLL generates the FMan clock from the platform PLL when operating synchronously, or from CC3 PLL

when operating asynchronously. Described in Section 3.1.8, “Frame Manager (FMan) clock select.”

•

Each of the four SerDes blocks has a PLL which generate a core clock from their respective externally supplied

SD_REF_CLKn/SD_REF_CLKn inputs. The frequency ratio is selected using the SerDes PLL ratio configuration bits

as described in Section 3.1.6, “Frequency options.”

Bit error ratio

BER

—

10-12

——

Unit Interval: 1.25 GBaud

800 – 100 ppm

800

800 + 100 ppm

Unit Interval: 3.125 GBaud

320 – 100 ppm

320

320 + 100 ppm

Notes:

1. Measured at receiver

2. See the RapidIOTM 1

×/4× LP Serial Physical Layer Specification for interpretation of jitter specifications.

3. Total jitter is composed of three components: deterministic jitter, random jitter, and single frequency sinusoidal jitter. The

sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 44. The sinusoidal jitter component

is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.

Table 93. SGMII receive AC timing specifications (continued)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

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