P5021 datasheet(116/155 Pages) NXP

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P5021 QorIQ Integrated Processor Data Sheet, Rev. 1

Electrical characteristics

Freescale Semiconductor

116

2.20.5.2.1

AC requirements for XAUI SD_REF_CLKn and SD_REF_CLKn

This table specifies AC requirements for SD_REF_CLKn and SD_REF_CLKn, where n = [2:3]. Only SerDes banks 2–3 may

be used for various SerDes XAUI configurations based on the RCW Configuration field SRDS_PRTCL. XAUI is not supported

on SerDes bank 1.

2.20.5.2.2

XAUI transmitter AC timing specifications

This table defines the XAUI transmitter AC timing specifications. RefClk jitter is not included.

Table 72. XAUI AC SD_REF_CLKn and SD_REF_CLKn input clock requirements (SVDD = 1.0 V)

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

Notes

SD_REF_CLK/SD_REF_CLK frequency range

tCLK_REF

—

125/

156.25

—MHz

—

SD_REF_CLK/SD_REF_CLK clock frequency

tolerance

tCLK_TOL

–100

—

100

ppm

—

SD_REF_CLK/SD_REF_CLK reference clock duty

cycle

tCLK_DUTY

SD_REF_CLK/SD_REF_CLK cycle to cycle jitter

(period jitter at refClk input)

tCLK_CJ

—

100

—

SD_REF_CLK/SD_REF_CLK total reference clock

jitter (peak-to-peak phase jitter at refClk input)

tCLK_PJ

-50

—

SD_REF_CLK/SD_REF_CLK rising/falling edge rate

tCLKRR/tCLKFR

1—4

V/ns

Differential input high voltage

VIH

200

—

Differential input low voltage

VIL

—

–200

Rising edge rate (SD_REF_CLKn) to falling edge rate

(SD_REF_CLKn) matching

Rise-Fall

Matching

——

3, 4

Notes:

1. Measured from –200 mV to +200 mV on the differential waveform (derived from SD_REF_CLKn – SD_REF_CLKn). The

signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is

centered on the differential zero crossing. See Figure 40.

2. Measurement taken from differential waveform

3. Measurement taken from single-ended waveform

4. Matching applies to rising edge for SD_REF_CLKn and falling edge rate for SD_REF_CLKn. It is measured using a 200 mV

window centered on the median cross point where SD_REF_CLKn rising meets SD_REF_CLKn falling. The median cross

point is used to calculate the voltage thresholds that the oscilloscope uses for the edge rate calculations. The rise edge rate

of SD_REF_CLKn should be compared to the fall edge rate of SD_REF_CLKn, the maximum allowed difference should not

exceed 20% of the slowest edge rate. See Figure 41.

Table 73. XAUI transmitter AC timing specifications

For recommended operating conditions, see Table 3.

Parameter

Symbol

Min

Typical

Max

Unit

Notes

Deterministic jitter

—

0.17

UI p-p

—

Total jitter

—

0.35

UI p-p

—

Unit Interval: 3.125 GBaud

320 – 100 ppm

320

320 + 100 ppm

—

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