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IMX6SDLCEC датащи(PDF) 110 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 110 Page - NXP Semiconductors |
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110 / 169 page ![]() i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 110 NXP Semiconductors Electrical Characteristics 4.11.12.6 High-Speed Clock Timing Figure 70. DDR Clock Definition 4.11.12.7 Forward High-Speed Data Transmission Timing The timing relationship of the DDR Clock differential signal to the Data differential signal is shown in Figure 71: Figure 71. Data to Clock Timing Definitions Model Parameters used for Driver Load switching performance evaluation CPAD Equivalent Single ended I/O PAD capacitance. —— — 1 pF CPIN Equivalent Single ended Package + PCB capacitance. —— — 2 pF LS Equivalent wire bond series inductance — — — 1.5 nH RS Equivalent wire bond series resistance — — — 0.15 Ω RL Load resistance — 80 100 125 Ω Table 71. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit |
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