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IMX6SDLCEC датащи(PDF) 109 Page - NXP Semiconductors |
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IMX6SDLCEC датащи(HTML) 109 Page - NXP Semiconductors |
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109 / 169 page ![]() Electrical Characteristics i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018 NXP Semiconductors 109 FDDRCLK DDR CLK frequency On DATAP/N outputs. 40 — 500 MHz PDDRCLK DDR CLK period 80 Ω<= RL< = 125 Ω 2 — 25 ns tCDC DDR CLK duty cycle tCDC = tCPH / PDDRCLK —50— % tCPH DDR CLK high time — — 1 — UI tCPL DDR CLK low time — — 1 — UI — DDR CLK / DATA Jitter — — 75 — ps pk–pk tSKEW[PN] Intra-Pair (Pulse) skew — — 0.075 — UI tSKEW[TX] Data to Clock Skew — 0.350 — 0.650 UI tr Differential output signal rise time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps tf Differential output signal fall time 20% to 80%, RL = 50 Ω 150 — 0.3UI ps ΔVCMTX(HF) Common level variation above 450 MHz 80 Ω<= RL< = 125 Ω —— 15 mVrms ΔVCMTX(LF) Common level variation between 50 MHz and 450 MHz. 80 Ω<= RL< = 125 Ω —— 25 mVp LP Line Drivers AC Specifications trlp,tflp Single ended output rise/fall time 15% to 85%, CL<70 pF — — 25 ns treo 30% to 85%, CL<70 pF — — 35 ns δV/δt SR Signal slew rate 15% to 85%, CL<70 pF — — 120 mV/ns CL Load capacitance — 0 — 70 pF HS Line Receiver AC Specifications tSETUP[RX] Data to Clock Receiver Setup time — 0.15 — — UI tHOLD[RX] Clock to Data Receiver Hold time — 0.15 — — UI ΔVCMRX(HF) Common mode interference beyond 450 MHz — — — 200 mVpp ΔVCMRX(LF) Common mode interference between 50 MHz and 450 MHz. —-50 — 50 mVpp CCM Common mode termination — — — 60 pF LP Line Receiver AC Specifications eSPIKE Input pulse rejection — — 300 Vps TMIN Minimum pulse response — 50 — ns VINT Pk-to-Pk interference voltage — — — 400 mV fINT Interference frequency — 450 — — MHz Table 71. Electrical and Timing Information (continued) Symbol Parameters Test Conditions Min Typ Max Unit |
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