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IMX6SDLCEC датащи(PDF) 107 Page - NXP Semiconductors

номер детали IMX6SDLCEC
подробное описание детали  i.MX 6Solo/6DualLite Applications Processors for Consumer Products
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производитель  NXP [NXP Semiconductors]
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IMX6SDLCEC датащи(HTML) 107 Page - NXP Semiconductors

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Electrical Characteristics
i.MX 6Solo/6DualLite Applications Processors for Consumer Products, Rev. 9, 11/2018
NXP Semiconductors
107
4.11.12.2 MIPI D-PHY Signaling Levels
The signal levels are different for differential HS mode and single-ended LP mode. Figure 67 shows both
the HS and LP signal levels on the left and right sides, respectively. The HS signaling levels are below
the LP low-level input threshold such that LP receiver always detects low on HS signals.
Figure 67. D-PHY Signaling Levels
ZID
Differential input impedance
—
80
—
125
Ω
LP Line Receiver DC Specifications
VIL
Input low voltage
—
—
—
550
mV
VIH
Input high voltage
—
920
—
—
mV
VHYST
Input hysteresis
—
25
—
—
mV
Contention Line Receiver DC Specifications
VILF
Input low fault threshold
—
200
—
450
mV
Table 70. Electrical and Timing Information (continued)
Symbol
Parameters
Test Conditions
Min
Typ
Max
Unit
HS Vout
Range
HS Vcm
Range
Max VOD
Min VOD
VCMTX,MIN
VOLHS
VCMTX,MAX
VOHHS
LP VIL
LP
VOL
LP
VIH
VOH,MAX
VOH,MIN
VIH
VIL
LP Threshold
Region
VGNDSH,MA
X
VGNDSH,MIN
GND
LP VOL
HS Differential Signaling
LP Single-ended Signaling



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