XRT7250 datasheet(137/463 Pages) EXAR

137 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

118

Writing a “1” to this bit-field configures the Framer to

automatically disable a given interrupt, following its

activation. Writing a “0” to this bit-field configures the

Framer to leave the Interrupt Enable bit as is, follow-

ing interrupt activation.

If a user opts to implement the Automatic Reset of In-

terrupt Enable Bits feature, then he/she might wish to

configure the Microprocessor/Microcontroller to go

back and re-enable these interrupts at a later time.

2.6.2

One-Second Interrupts

The Block Interrupt Status register, and Block Inter-

rupt Enable register each contain a bit-field for the

One-Second Interrupt. If this interrupt is enabled

(within the Block Interrupt Enable register), then the

Framer device will automatically generate an interrupt

request to the Microprocessor/Microcontroller repeat-

edly at one-second intervals. At a minimum, the us-

er’s interrupt service routine must service this inter-

rupt by reading the Block Interrupt Status register

(Address = 0x05). Once the Microprocessor/Micro-

controller has read this register, then the following

things will happen.

1. The One-Second Interrupt bit-field, within the

Block Interrupt Status register, will be reset to “0”.

2. The Framer will negate the INT (Interrupt

Request) output pin.

The purpose of providing this One-Second interrupt is

to allow the Microprocessor/Microcontroller the op-

portunity to perform certain tasks at One-Second in-

tervals. The user can accomplish this by including

the necessary code (for these various tasks) as a part

of the interrupt service routine, for the One-Second

type interrupt. Some of these tasks could include:

• Reading in the contents of the One-Second Perfor-

mance Monitor registers.

• Reading various other Performance Monitor regis-

ters.

• Writing a new PMDL Message into the Transmit

LAPD Message buffer. After the LAPD Transmitter

has been enabled and commanded to initiate trans-

mission of the LAPD Message frame (containing

the PMDL Message, residing within the Transmit

LAPD Message buffer), the LAPD Transmitter will

continue to re-transmit this same LAPD Message

frame, repeatedly at One-Second intervals, until it

has been disabled. If a new PMDL message is

written into the Transmit LAPD Message buffer

immediately following the occurrence of a One-Sec-

ond Interrupt, then this will ensure that this Write

activity will not interfere with this periodic transmis-

sion of the LAPD Message frames.

Notes regarding the Block Interrupt Enable and Block

Interrupt Status Registers:

1. The Block Interrupt Enable Register allows the

user to globally disable all potential interrupts

within either the Transmit or Receive sections, by

writing a “0” into the appropriate bit-field of this

all potential interrupts within a given functional

block. In other words, enabling a given functional

block does not automatically enable all of its

potential interrupt sources. Those potential inter-

rupt sources that have been disabled at the

source level will remain disabled, independent of

the status of their associated functional blocks.

2. The Block Interrupt Enable register is set to

“0x00” upon power or reset. Therefore, the user

will have to write some “1’s” into this register, in

order to enable some of the interrupts.

The remaining registers, listed in Table 9, Table 10

and Table 11 will be presented in the discussion of

the functional blocks, within the XRT7250 Framer IC.

These discussions will present more details about the

interrupt causes and how to properly service. them.

2.7

INTERFACING THE FRAMER TO AN INTEL-TYPE

MICROPROCESSOR

The Framer can be interfaced to either Intel-type or

Motorola-type Microprocessor/Microcontrollers. The

following sections will provide one example for each

type of processor. This section discusses how to in-

terface the XRT7250 DS3/E3 Framer IC to the 8051

Microcontroller.

FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00)

BIT 7BIT 6BIT 5BIT 4

BIT 3BIT 2BIT 1BIT 0

Local

Loop-Back

DS3/E3

Internal

LOS Enable

RESET

Interrupt

Enable Reset

Frame Format

TimRefSel[1:0]

R/W

000

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