XRT7250 datasheet(70/463 Pages) EXAR

70 / 463 page

áç

DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

b. The input drivers of the bi-directional data bus are

enabled.

NOTE: In order to insure that the XRT7250 DS3/E3 Framer

device will interpret this signal as being a Write signal, the

µC/µP should keep the WR_RW input pin "Low".

B.3

After some settling time, the data, in the inter-

nal data bus, will stabilize and is ready to be

latched into the Framer Microprocessor Inter-

face block. The Microprocessor Interface block

will indicate that this data is ready to be latched

by asserting the RDY_DTCK (DTACK) output

signal. At this point, the µC/µP should latch the

data into the Framer by toggling the RD_DS

input pin "High".

For subsequent write operations, within this burst I/O

access, the µC/µP simply repeats steps B.1 through

B.3 as illustrated in Figure 36.

2.2.2.2.2.2.3

Terminating the Burst I/O Access

The Burst I/O Access will be terminated upon the fall-

ing edge of the ALE_AS input signal. At this point the

Framer will cease to internally increment the latched

address value. Further, the µC/µP is now free to exe-

cute either a Programmed I/O access or to start an-

other Burst I/O Access with the XRT7250 DS3/E3

Framer.

2.3

ON-CHIP REGISTER ORGANIZATION

The Microprocessor Interface section, within the

Framer device allows the user to do the following.

• Configure the Framer into a wide variety of operat-

ing modes.

• Employ various features of the Framer device.

• Perform status monitoring

• Enable/Disable and service Interrupt Conditions

All of these things are accomplished by reading from

and writing to the many on-chip registers within the

Framer device. Table 4 lists each of these registers

and their corresponding address locations within the

Framer Address space.

2.3.1

Framer Register Addressing

The array of on-chip registers consists of a variety of

Table 4, as follows.

R/O - Read Only Registers.

R/W - Read/Write Registers

RUR - Reset-upon-Read Registers

Additionally, some of these registers consists of both

R/O and R/W bit-fields. These registers are denoted

in Table 4 as Combination of R/W and R/O.

The bit-format and definitions for each of these regis-

ters are presented in Section 3.3.2

FIGURE 36. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT WRITE OPERATIONS

WITH THE

BURST I/O CYCLE (MOTOROLA-TYPE µC/µP)

ALE_AS

RD_DS

A[8:0]

D[15:0]

RDY_DTCK

Data Written at Offset =0x01

WR_RW

Data Written at Offset =0x02

Address of “Initial” Target Register (Offset = 0x00)

XRT7250 датащи(PDF) 70 Page - Exar Corporation

XRT7250 датащи(HTML) 70 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL