XRT7250 datasheet(63/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

áç

REV. 1.1.1

munication between the µC/µP and the Framer

Microprocessor Interface block.

A.3

Assert the ALE_AS (Address Latch Enable) pin

by toggling it "High". This step enables the

Address Bus input drivers, within the Micropro-

cessor Interface block of the Framer.

A.4

After allowing the data on the Address Bus pins

to settle (by waiting the appropriate Address

Data Setup time), the µC/µP should then toggle

the ALE_AS pin "Low". This step latches the

contents, on the Address Bus pins, A[8:0], into

the XRT7250 DS3/E3 Framer Microprocessor

Interface block. At this point, the initial address

of the burst access has now been selected.

NOTE: The ALE_AS input pin should remain "Low" for the

remainder of this Burst Access operation.

A.5

Next, the µC/µP should indicate that this cur-

rent bus cycle is a Read Operation by toggling

the RD_DS (Read Strobe) input pin "Low".

This action also enables the bi-directional data

bus output drivers of the Framer device. At this

point, the bi-directional data bus output drivers

will proceed to drive the contents of the

addressed register onto the bi-directional data

bus, D[7:0].

A.6

Immediately after the µC/µP toggles the Read

Strobe signal "Low", the Framer device will tog-

gle the RDY_DTCK (READY) output pin "Low".

The Framer device does this in order to inform

the µC/µP that the data (to be read from the

data bus) is NOT READY to be latched into the

µC/µP.

A.7

After some settling time, the data on the bi-

directional data bus will stabilize and can be

read by the µC/µP. The XRT7250 DS3/E3

Framer will indicate that this data is ready to be

read, by toggling the RDY_DTCK (Ready) sig-

nal "High".

A.8

After the µC/µP detects the RDY_DTCK signal

(from the XRT7250 DS3/E3 Framer IC), it can

then will terminate the Read cycle by toggling

the RD_DS (Read Strobe) input pin "High".

Figure 29 presents an illustration of the behavior of

the Microprocessor Interface Signals, during the initial

Read Operation, within a Burst I/O Cycle for an Intel-

type µC/µP.

At the completion of this initial read cycle, the µC/µP

has read in the contents of the first register or buffer

location (within the XRT7250 DS3/E3 Framer) for this

particular burst I/O access operation. In order to illus-

trate how this burst access operation works, the byte

(or word) of data, that is being read in Figure 29, has

been labeled Valid Data at Offset = 0x00. This label

FIGURE 29. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A

BURST CYCLE (INTEL TYPE PROCESSOR)

ALE_AS

RD_DS

A[8:0]

D[15:0]

RDY_DTCK

Not Valid

Valid Data of Offset = 0x00

Address of “Initial” Target Register (Offset = 0x00)

WR_RW

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