XRT7250 datasheet(83/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

2.3.2.11 Receive DS3 FEAC Register

This Read/Write register contains the latest 6-bit

FEAC code that has been validated by the Receive

FEAC Processor. The contents of this register will be

cleared if the previously validated code has been re-

moved by the FEAC Processor.

NOTE: For more information on the operation of the

Receive FEAC Processor, please see Section 3.3.3.1.

2.3.2.12 Receive DS3 FEAC Interrupt Enable/

Status Register

Bit 4 - FEAC Valid

This Read Only bit is set to "1" when an incoming

FEAC Message Code has been validated by the Re-

ceive DS3 Framer. This bit is cleared to "0" when the

FEAC code is removed.

NOTE: For more information on the role of this bit-field and

the Receive FEAC Processor, please see Section 3.3.3.1.

Bit 3 - RxFEAC Remove Interrupt Enable

This Read/Write bit-field allows the user to enable/

disable the RxFEAC Removal interrupt. Writing a "1"

to this bit enables this interrupt. Likewise, writing a

"0" to this bit-field disables this interrupt.

NOTE: For more information on the role of this bit-field and

the Receive FEAC Processor, please see Section 3.3.3.1.

Bit 2 - RxFEAC Remove Interrupt Status

A "1" in this Read Only bit-field indicates that the last

validated FEAC Message has now been removed by

the Receive FEAC Processor. The Receive FEAC

Processor will remove a validated FEAC message if 3

out of the last 10 received FEAC messages differ

from the latest valid FEAC Message.

NOTE: For more information on this bit-field and the

Receive FEAC Processor, please see Section 3.3.3.1.

Bit 1 - RxFEAC Valid Interrupt Enable

This Read/Write bit-field allows the user to enable/

disable the Rx FEAC Valid interrupt. Writing a "1" to

this bit-field enables this interrupt. Whereas, writing a

"0" disables this interrupt. The value of this bit-field is

"0" following power up or reset.

NOTE: For more information on this bit-field and the

Receive FEAC Processor, please see Section 3.3.3.1.

Bit 0 - RxFEAC Valid Interrupt Status

A "1" in this Read Only bit-field indicates that a newly

received FEAC Message has been validated by the

Receive FEAC Processor.

NOTE: For more information on this bit-field and the

Receive FEAC Processor, please see Section 3.3.3.1.

RXDS3 FEAC REGISTER (ADDRESS = 0X16)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

RxFEAC[5:0]

Not Used

R/O

000

RXDS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

FEAC Valid

RxFEAC

Remove

Interrupt

Enable

RxFEAC

Remove

Interrupt

Status

RxFEAC

Valid

Interrupt

Enable

RxFEAC

Valid

Interrupt

Status

R/W

RUR

R/W

RUR

000

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