XRT7250 datasheet(136/463 Pages) EXAR

136 / 463 page

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

117

Once the Microprocessor/Microcontroller has read

the register that corresponds to the interrupting

source within the Framer, the following things will

happen.

1. The Asserted Interrupt Status bit-fields within this

2. The Asserted bit-field, within the Block Interrupt

Status register will be reset.

3. The Framer device will negate the INT (Interrupt

Request) output pin, by drving this output pin

"High”.

2.6.1

Automatic Reset of Interrupt Enable Bits

Occassionally, the user’s system (which includes the

Framer device) may experience a fault condition,

such that a Framer Interrupt Condition will continu-

ously exist. If this particular interrupt condition has

been enabled (within the Framer IC) then the Framer

device will generate an interrupt request to the MIcro-

processor/Microcontroller. Afterwards, the Micropro-

cessor/Microcontroller will attempt to service this in-

terrupt by reading the Block Interrupt Status register

and the subsequent source level interrupt status reg-

isters. Additionally, the Microprocessor/Microcontrol-

ler will attempl to perform some system-related tasks

in order to try to resolve those conditions causing the

interrupt. After the Microprocessor/Microcontroller

has attempted all of these things, the Framer IC will

negate the INT output pin. However, because the

system fault still remains, the conditions causing the

Framer to issue this interrupt request, also still exists.

Consequently, the Framer device will generate anoth-

er interrupt request, which forces the Microprocessor/

Microcontroller to once again attempt to service this

interrupt. This phenomenon quickly results in the lo-

cal Microprocessor/Microcontroller being tied up in a

continuous cycle of executing this one interrupt ser-

vice routine. Consequently, the local Microprocessor/

Microcontroller (along with portions of the overall sys-

tem) now becomes non-functional.

In order to prevent this phenomenon from ever occur-

ing, the Framer IC allows the user to automatically re-

set the interrupt enable bits, following their activation.

The user can implement this feature by writing the ap-

propriate value into Bit 3 (Interrupt Enable Reset)

within the Framer Operating Mode register, as illus-

trated below.

TABLE 10: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.832 APPLICATIONS)

INTERRUPTING

FUNCTIONAL BLOCK

THE NEXT REGISTERS TO BE READ DURING THE INTERRUPT SERVICE

ROUTINE

Receive Section

RxE3 Interrupt Status Register - 1

0 x 014

RxE3 Interrupt Status Register - 2

0 x 15

RxE3 LAPD Control Register

0 x 18

Transmit Section

TxE3 LAPD Status and Interrupt Register

0 x 34

TABLE 11: INTERRUPT SERVICE ROUTINE GUIDE (FOR E3, ITU-T G.751 APPLICATIONS)