XRT7250 datasheet(90/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

This Reset-upon-Read bit-field will be set to "1" if a

Receipt of New Trail Trace Buffer Message interrupt

has occurred since the last read of this register.

The Receive E3 Framer will generate the Receipt of

New Trail Trace Buffer Message interrupt, if it receives

an E3 frame in which the value of the TR byte-field is

of the form "1xxxxxxxb". A TR byte-field value of this

form is identified as the frame start marker.

NOTE: Please see Section 5.3.6.1.6 for a more detailed dis-

cussion of this interrupt.

Bit 4 - FEBE (Far-End Block Error) Interrupt Status

This Reset-upon-Read bit-field will be set to "1" if the

FEBE (Far-End-Block Error) interrupt has occurred

since the last read of this register.

The Receive E3 Framer will generate the FEBE inter-

rupt anytime it detects a "1" in the FEBE bit-field with-

in an incoming E3 frame.

NOTE: Please see Section 5.3.6.1.8 for a more detailed dis-

cussion of this interrupt.

Bit 3 - FERF Interrupt Status

This Reset Upon Read bit will be set to '1' if the Re-

ceive E3 Framer has detected a Change in the Rx

FERF Condition, since the last time this register was

read.

This bit-field will be asserted under either of the fol-

lowing two conditions.

1. When the Receive E3 Framer first detects the

occurrence of an RxFERF Condition (e.g., when

the FERF bit, within the last 3 or 5 consecutive

E3 frames are set to "1").

2. When the Receive E3 Framer detects the end of

the RxFERF Condition (e.g., when the FERF bit,

within the last 3 or 5 consecutive E3 frames are

set to "0").

NOTE: For more information on the RxFERF (Yellow Alarm)

condition, please see Section 5.3.2.6.3.

Bit 2 - EM (BIP-8) Byte Error Interrupt Status

This Reset-upon-Read bit-field will be set to "1" if the

BIP-8 Error interrupt has occurred since the last read

of this register.

The Receive E3 Framer will generate the BIP-8 Error

interrupt if it has concluded that it has received an er-

rored E3 frame, from the Far-End Terminal.

NOTE: Please see Section 5.3.6.1.9 for a more detailed dis-

cussion of this interrupt.

Bit 1 - Framing Byte Error Interrupt Status

This Reset-upon-Read bit-field will be set to "1" if the

Framing Byte Error interrupt has occurred since the

last read of this register.

The Receive E3 Framer will generate the Framing

Byte Error interrupt if it has detected an error in the

FA1 or FA2 bytes, on an incoming E3 frame.

NOTE: Please see Section 5.3.6.1.10 for a more detailed

discussion of this interrupt.

Bit 0 - Rx Pld Mis Interrupt Status

This Reset-upon-Read bit-field will be set to "1" if the

Payload Type Mismatch interrupt has occurred since

the last read of this register.

The Receive E3 Framer will generate the Payload

Type Mismatch interrupt when it detects that the val-

ues, within the Payload Type bit-fields of the incoming

E3 frame, has changed from that of the previous E3

frame.

NOTE: Please see Section 5.3.6.1.11 for a more detailed

discussion on this interrupt.

2.3.3.7

Receive E3 LAPD Control Register (E3,

ITU-T G.832)

Bit 3 - DL from NR

This Read/Write bit-field allows the user to specify

whether the LAPD Receiver should retrieve the bytes,

comprising the incoming LAPD Message frame, from

the NR byte-field, or from the GC byte-field, within

each incoming E3 frame.

Writing a "1" configures the LAPD Receiver to re-

trieve the incoming LAPD Message frame octets from

the NR byte-field, within each incoming E3 frame.

Writing a "0" configures the LAPD Receiver to re-

trieve the incoming LAPD Message frame octets from

the GC byte.

RXE3 LAPD CONTROL REGISTER (ADDRESS = 0X18)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

DL from NR

RxLAPD

Enable

RxLAPD

Interrupt

Enable

RxLAPD

Interrupt

Status

R/W

RUR

0000

000

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