XRT7250 datasheet(19/463 Pages) EXAR

19 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

XVII

LIST OF TABLES

Table 1:Description of the Microprocessor Interface Signals that exhibit constant roles in both the Intel and Mo-

torola Modes ................................................................................................................................................... 37

Table 2:Pin Description of Microprocessor Interface Signals - While the Microprocessor Interface is Operating

in the Intel Mode ............................................................................................................................................. 37

Table 3:Pin Description of the Microprocessor Interface Signals while the Microprocessor Interface is operating

in the Motorola Mode ...................................................................................................................................... 38

Table 4:Register Addressing of the Framer Programmer Registers ............................................................... 52

Table 5:List of all of the Possible Conditions that can Generate Interrupts within the XRT7250 Framer Device

114

Table 6:A Listing of the XRT7250 Framer Device Interrupt Block Registers (for DS3 Applications) ............ 114

Table 7:A Listing of the XRT7250 Framer Device Interrupt Block Registers (for E3, ITU-T G.832 Applications)

114

Table 8:A Listing of the XRT7250 Framer Device Interrupt Block Register (for E3, ITU-T G.751 Applications) ..

115

Table 9:Interrupt Service Routine Guide (for DS3 Applications) ................................................................... 116

Table 10:Interrupt Service Routine Guide (for E3, ITU-T G.832 Applications) ............................................. 117

Table 11:Interrupt Service Routine Guide (for E3, ITU-T G.751 Applications) ............................................. 117

Table 12:Alternate Functions of Port 3 Pins ................................................................................................. 119

Table 13:Interrupt Service Routine Location (in Code Memory) for the INT0* and INT1* Interrupt Input pins ....

120

Table 14:Auto-Vector Table for the MC68000 Microprocessor ..................................................................... 122

Table 15:The Relationship between the states of RLOOP, LLOOP and the resulting loop-back mode with the

XRT7300 device ........................................................................................................................................... 125

Table 16:The Relationship between the content of Bit 2, (C-Bit Parity*/M13) within the Framer Operating Mode

Register and the resulting DS3 Framing Format ........................................................................................... 128

Table 17:C-bit Functions for the C-bit Parity DS3 Frame Format ................................................................. 129

Table 18:Listing and Description of the pins associated with the Transmit Payload Data Input Interface .... 134

Table 19:A Listing of the Overhead bits within the DS3 frame, and their potential sources, within the XRT7250

IC .................................................................................................................................................................. 150

Table 20:Description of Method 1 Transmit Overhead Input Interface Signals ............................................. 151

Table 21:The Relationship between the Number of Rising Clock Edges in TxOHClk, (since TxOHFrame was

last sampled "High") to the DS3 Overhead Bit, that is being processed ....................................................... 153

Table 22:Description of Method 2 Transmit Overhead Input Interface Signals ............................................. 156

Table 23:The Relationship between the Number of TxOHEnable pulses (since the last occurrence of the TxO-

HFrame pulse) to the DS3 Overhead Bit, that is being processed by the XRT7250 .................................... 158

Table 24:The LAPD Message Type and the Corresponding value of the First Byte, within the Information Pay-

load ............................................................................................................................................................... 163

Table 25:Relationship between TxLAPD Msg Length and the LAPD Message Size .................................... 164

Table 26:Relationship between TxLAPD Msg Length and the LAPD Message Size .................................... 164

Table 27:The Relationship between the contents of Bit 7 (Tx Yellow Alarm) within the Tx DS3 Configuration Reg-

ister, and the resulting Transmit DS3 Framer Block's Action ........................................................................ 169

Table 28:The Relationship between the contents of Bit 6 (Tx X-Bits) within the Tx DS3 Configuration Register,

and the resulting Transmit DS3 Framer Block's Action ................................................................................. 170

Table 29:The Relationship between the contents of Bit 5 (Tx Idle) within the Tx DS3 Configuration Register, and

the resulting Transmit DS3 Framer Action .................................................................................................... 170

Table 30:The Relationship between the contents of Bit 4 (Tx AIS Pattern) within the Tx DS3 Configuration Reg-

ister, and the resulting Transmit DS3 Framer Block's Action ........................................................................ 171

Table 31:The Relationship between the contents of Bit 3 (Tx LOS) within the Tx DS3 Configuration Register,

and the resulting Transmit DS3 Framer Block's Action ................................................................................. 171

Table 32:The Relationship between the content of Bit 3 (Unipolar/Bipolar*) within the UNI I/O Control Register

and the Transmit DS3 Framer Line Interface Output Mode .......................................................................... 176

Table 33:The Relationship between Bit 4 (AMI/B3ZS*) within the I/O Control Register and the Bipolar Line Code

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