XRT7250 datasheet(88/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

2.3.3.4

3.3.2.18 Receive E3 Interrupt Enable

Bit 6 - TTB Change Interrupt Enable

This Read/Write bit-field allows the user to enable or

disable the Change in Trail Trace Buffer Message in-

terrupt. Setting this bit-field to "1" enables this inter-

rupt. Setting this bit-field to "0" disables this interrupt.

NOTE: For more information on Trail Trace Buffer mes-

sages, please see Section 5.3.2.9.

Bit 5 - Received LAPD Message Interrupt Enable

This Read/Write bit-field allows the user to enable or

disable the Received LAPD Message frame interrupt.

Setting this bit-field to "1" enables this interrupt. Set-

ting this bit-field to "0" disables this interrupt.

NOTE: For more information on this interrupt, please see

Section 5.3.6.1.12.

Bit 4 - FEBE (Far-End Block Error) Interrupt En-

able

This Read/Write bit-field allows the user to enable or

disable the Far-End-Block Error (FEBE) interrupt.

Setting this bit-field to "1" enables this interrupt. Set-

ting this bit-field to "0" disables this interrupt.

NOTE: For more information on the FEBE Interrupt condi-

tion, please see Section 5.3.6.1.8.

Bit 3 - FERF (Far-End Receive Failure) Interrupt

Enable

This Read/Write bit-field allows the user to enable or

disable the Change in FERF Condition interrupt. Set-

ting this bit-field to "1" enables this interrupt. Setting

this bit-field to "0" disables this interrupt.

NOTE: For more information on the Change in FERF Condi-

tion interrupt, please see Section 5.3.6.1.7.

Bit 2 - EM Byte Error Interrupt Enable

This Read/Write bit-field allows the user to enable or

disable the EM Byte Error interrupt. Setting this bit-

field to "1" enables this interrupt. Setting this bit-field

to "0" disables this interrupt.

NOTE: For more information on this interrupt, please see

Section 5.3.6.1.9.

Bit 1 - Framing Byte Error Interrupt Enable

This Read/Write bit-field allows the user to enable or

disable the Framing Byte Error interrupt. Setting this

bit-field to "1" enables this interrupt. Setting this bit-

field to "0" disables this interrupt.

NOTE: For more information on this interrupt, please see

Section 5.3.6.1.10.

Bit 0 - Receive Payload Type Mismatch Interrupt

Enable

This Read/Write bit-field allows the user to enable or

disable the Receive Payload Type Mismatch interrupt.

Setting this bit-field to "1" enables this interrupt. Set-

ting this bit-field to "0" disables this interrupt.

NOTE: For more information on this interrupt, please see

Section 5.3.6.1.11.

2.3.3.5

Receive E3 Interrupt Status Register -

1 (E3, ITU-T G.832)

RXE3 INTERRUPT ENABLE REGISTER - 2 (ADDRESS = 0X13)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

TTB

Change

Interrupt

Enable

Not Used

FEBE

Interrupt

Enable

FERF

Interrupt

Enable

BIP-8

Error Interrupt

Enable

Framing

Byte Error

Interrupt

Enable

RxPld

Mis

Interrupt

Enable

R/W

0000

000

RXE3 INTERRUPT STATUS REGISTER - 1 (ADDRESS = 0X14)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

COFA

Interrupt

Status

OOF

Interrupt

Status

LOF

Interrupt

Status

LOS

Interrupt

Status

AIS

Interrupt

Status

RUR

0000

000

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