XRT7250 datasheet(141/463 Pages) EXAR

141 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

122

Functional Description of Circuit illustrated in

Figure 38.

When the XRT7250 DS3/E3 Framer IC generates an

Interrupt, the INT output will toggle "Low”. This will

force Input 6, of the Interrupt Priority Encoder chip

(U4) to also toggle "Low”. In response to this, the In-

terrupt Priority Encoder chip will set its three outputs

to the following states: A2 = ‘0’, A1 = ‘0’ and A0 = ‘1’

(which is the number 6 in Highinverted binary format).

The state of three output pins will be read by the ac-

tive-low interrupt request inputs of the Microprocessor

(IPL2, IPL1, IPL0). When the MC68000 Microproces-

sor detects this value at its three interrupt request in-

puts, it will know two things.

1. An interrupt request has been issued by one of

the peripheral devices.

2. The interrupt request is a Level 6 interrupt

request (due to the values of the A2 - A0 outputs

from the Interrupt Priority Encoder IC).

Once the MC68000 Microprocessor has determined

these two things it will initiate an Interrupt Acknowl-

edge (IACK) cycle by doing the following:

1. Identify this new bus cycle as an interrupt service

routine by setting all of its Function Code output

pins (FC2 - FC0) to "High”.

2. Placing the interrupt level on the Address output

pins A[3:1].

When the MC68000 Microprocessor has toggled all

of its Function Code output pin "High”, the Function

Code Decoder chip (U3) will read this value from the

FC2 - FC0 pins as being the binary value for 7. As a

result, U3 will assert its active-low Y7 output pin. At

the same time, the address lines A[3:1] are carrying

the current Interrupt Level of this IACK cycle (level =

6, or “110” in this example) and applying this value to

the A, B, and C inputs of the IACK Level Decoder chip

(U5). Initially, all of the outputs of U5 are tri-stated.

Due to the fact that its active-low G2A and G2B inputs

are negated (e.g., at a logic "High”). However, when

the MC68000 Microprocessor begins the IACK cycle,

it will assert its Address Strobe (AS*) signal. This ac-

tion will result in asserting the G2A input pin of U5.

Additionally, since the Function Code Decoder chip

has also asserted its Y7 output pin this will, in turn,

assert the G2A input pin of U5. At this point, the out-

put of U5 will no longer be tri-stated. U5 will read in

the contents of its A, B, and C inputs, and assert the

active-low VPA* (Valid Peripheral Address) input pin

of the MC68000. Anytime the MC68000 detects its

VPA* pin being asserted during an IACK cycle, it

knows that this is an Auto-Vectored Interrupt cycle.

Further, it also knows that it will not receive an inter-

rupt vector from the peripheral device (e.g., the

XRT7250 DS3/E3 Framer IC, in this case), and that it

must generate its own vector. In the very next bus cy-

cle, the MC68000 is going to implement a pseudo-

read of the data bus. However, in reality, no data will

be read from the XRT7250. The MC68000 will in-

stead have determined that since this current IACK

cycle is an Auto-Vectored - Level 6 Interrupt cycle,

which corresponds to Vector Number 30, within the

MC68000’s Exception Vector Table. Vector Number

30 corresponds to an Address Space of 0x78, in the

MC68000’s address space. In the case of this exam-

ple, the user is required to place an unconditional

branch statement (to the location of the XRT7250 In-

terrupt Service Routine) at 0x78 in system memory.

Table 14 presents the Auto-Vector Table (e.g., the re-

lationship between the Interrupt Level and the corre-

sponding location in memory for this unconditional

branch statement) for the MC68000 Microprocessor.

3.0

THE LINE INTERFACE AND SCAN SECTION

TABLE 14: AUTO-VECTOR TABLE FOR THE MC68000 MICROPROCESSOR

INTERRUPT

LEVEL

VECTOR NUMBER

ADDRESS LOCATION (OF UNCONDITIONAL BRANCH INSTRUCTION - FOR INTERRUPT

SERVICE ROUTINE)

125

0x064

226

0x068

327

0x06C

428

0x070

529

0x074

630

0x078

731

0x07C

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