XRT7250 datasheet(82/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

cally, the Receive DS3 Framer will assert this bit-field

under either of the following two conditions:

1. When the Receive DS3 Framer detects the onset

of the Idle Condition and

2. When the Receive DS3 Framer detects the end

of the Idle Condition.

The local µP can determine the current state of the

Idle condition by reading bit 5 of the Rx DS3 Configu-

ration and Status Register (Address = 0x10).

NOTE: For more information into the Idle Condition, please

see Section 3.3.2.5.3.

Bit 3 - FERF Interrupt Status

This Reset Upon Read bit will be set to '1' if the Re-

ceive DS3 Framer has detected a Change in the Rx

FERF Condition, since the last time this register was

read.

This bit-field will be asserted under either of the fol-

lowing two conditions.

1. When the Receive DS3 Framer first detects the

occurrence of an Rx FERF Condition (all X-bits

are set to '0').

2. When the Receive DS3 Framer detects the end

of the Rx FERF Condition (all X-bits are set to

'0').

The local microprocessor can determine the current

state of the FERF Condition by reading bit 4, within

the Rx DS3 Status Register (Address = 0x11).

NOTE: For more information on the Rx FERF (Yellow

Alarm) condition, please see Section 3.3.2.5.4.

Bit 2 - (Change in) AIC Interrupt Status

This Reset Upon Read bit-field is set to "1" if the AIC

bit-field, within the incoming DS3 frames, has

changed state since the last read of this register.

NOTE: For more information on this interrupt condition,

please see Section 3.3.2.5.6.

Bit 1 - OOF Interrupt Status

This Reset Upon Read bit-field is set to "1" if the Re-

ceive DS3 Framer has detected a Change in the Out-

of-Frame (OOF) Condition, since the last time this

serted under either of the following two conditions:

1. When the Receive DS3 Framer has detected the

appropriate conditions to declare an OOF Condi-

tion.

2. When the Receive DS3 Framer has transitioned

from the OOF Condition (Frame Acquisition

Mode) into the In-Frame Condition (Frame Main-

tenance mode).

NOTE: For more information of the OOF Condition, please

see Section 3.3.2.2.

Bit 0 - P-Bit Error Interrupt Status

This Reset Upon Read bit-field indicates whether or

not the Detection of P-bit error interrupt has occurred

since the last read of this register. This bit-field will

be "0" if the Detection of P-bit error interrupt has NOT

occurred since the last read of this register. This bit-

field will be set to "1", if this interrupt has occurred

since the last read of this register. The Detection of

P-bit Error interrupt will occur if the Receive DS3

Framer Block detects a P-bit error in the incoming

DS3 frame.

NOTE: For more information into the role of P-bits please

see Section 3.3.2.6.1.

3.3.2.11 Receive DS3 Sync Detect Enable Register

RxDS3 Sync Detect Enable Register (Address =

0x14)

Bits 4 - 0 Enable5 F(4)- F(0)

These Read/Write bit-fields allows the user to enable

or disable the 5 parallel searches for valid M and F-

bit, while the Receive DS3 Framer is operating in the

Frame Acquisition mode. For proper operation, the

user is highly encouraged to ensure that all of these

bit-fields are set to "1".

RXDS3 SYNC DETECT ENABLE REGISTER (ADDRESS = 0X14)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

Not Used

Enable F[4]

Enable F[3]

Enable F[2]

Enable F[1]

Enable F[0]

R/W

0011

111

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