XRT7250 datasheet(62/463 Pages) EXAR

62 / 463 page

áç

DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

2.2.2.2

Data Access using Burst Mode I/O

Burst Mode I/O access is a much faster way to trans-

fer data between the µC/µP and the Microprocessor

Interface (of the XRT7250 DS3/E3 Framer), than Pro-

grammed I/O. The reason why Burst Mode I/O is

faster is explained below.

Data is placed upon the Address Bus input pins

A[8:0] only for the very first access, within a given

burst access. The remaining read or write operations

(within this burst access) do not require the place-

ment of the Address Data on the Address Data Bus.

As a consequence, the user does not have to wait

through the Address Setup and Hold times for each of

these Read/Write operation, within the Burst Access.

It is important to note that there are some limitations

associated with Burst Mode I/O Operations.

1. All cycles within the Burst Access, must be either

all Read or all Write cycles. No mixing of Read

and Write cycles is permitted.

2. A Burst Access can only be used when Read or

Write operations are to be employed over a con-

tiguous range of address locations, within the

Framer device.

3. The very first Read or Write cycle, within a burst

access, must start at the lowest address value, of

the range of addresses to be accessed. Subse-

quent operations will automatically be incre-

mented to the very next higher address value.

Examples of Burst Mode I/O operations are present-

ed below for read and write operations, with both In-

tel-type and Motorola-type µC/µP.

2.2.2.2.1

Burst I/O Access in the Intel Mode

If the XRT7250 DS3/E3 Framer is interfaced to an In-

tel-type µC/µP (e.g., the 80x86 family, etc.), then it

should be configured to operate in the Intel mode (by

tying the MOTO pin to ground). Intel-type Read and

Write Burst I/O Access operations are described be-

low.

2.2.2.2.1.1

The Intel-Mode Read Burst Access

Whenever an Intel-type µC/µP wishes to read the

contents of numerous registers or buffer locations

over a contiguous range of addresses, then it should

do the following.

Perform the initial read operation of the burst

access.

b. Perform the remaining read operations of the

burst access.

c. Terminate the burst access operation.

Each of these operations within the burst access are

described below.

2.2.2.2.1.1.1

The Initial Read Operation

The initial read operation of an Intel-type read burst

access is accomplished by executing a Programmed

I/O Read Cycle as summarized below.

A.0

Execute a Single Ordinary (Programmed I/

O) Read Cycle, as described in steps A.1

through A.7 below.

A.1

Place the address of the initial-target register or

buffer location (within the Framer) on the

Address Bus input pins A[8:0].

A.2

While the µC/µP is placing this address value

onto the Address Bus, the Address Decoding

circuitry (within the user's system) should

assert the CS input pin of the Framer, by tog-

gling it "Low". This step enables further com-

FIGURE 28. ILLUSTRATION OF THE BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNAL, DURING A MOTOROLA-

TYPE

PROGRAMMED I/O WRITE OPERATION

ALE_AS

A[8:0]

D[15:0]

RD_DS

RDY_DTCK

Data to be Written

Address of Target Register

WR_RW

XRT7250 датащи(PDF) 62 Page - Exar Corporation

XRT7250 датащи(HTML) 62 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL