XRT7250 datasheet(78/463 Pages) EXAR

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DS3/E3 FRAMER IC

XRT7250

REV. 1.1.1

Setting this bit-field to "1" enables the Transmit Sec-

tion related Interrupts (within the XRT7250) at the

block level.

NOTE: Setting this bit-field to "1" does not enable all Trans-

mit Section related Interrupts. Each of these interrupts can

still be disabled at the Source Level. However, setting this

bit-field to "0" does disable all Transmit Section related

Interrupts.

Bit 0 - One-Second Interrupt Enable

This Read/Write bit-field permits the user to enable or

disable the One-Second Interrupt, within the

XRT7250. If this interrupt is enabled, then the

XRT7250 will generate interrupts to the µC/µP at one-

second intervals.

Setting this bit-field to "0" disables the One-Second

Interrupt. Conversely, setting this bit-field to "1" en-

ables the One-Second Interrupt.

2.3.2.6

Block Interrupt Status Register

Bit 7 - RxDS3/E3 Interrupt Status Indicator

This Read-Only bit-field indicates whether or not a

Receive-Section related interrupt has been requested

and is awaiting service.

If this bit-field is set to "0", then there are no Receive-

Section related interrupts awaiting service. Con-

versely, if this bit-field is set to "1", then there is at

least one Receive Section related interrupt, awaiting

service.

NOTE: If this bit-field is set to "1", then the

µC/µP must

read the Source-Level Interrupt Status register, in order to

clear this bit-field.

Bit 1 - TxDS3/E3 Interrupt Status Indicator

This Read-Only bit-field indicates whether or not a

Transmit-Section related interrupt has been request-

ed and is awaiting service.

If this bit-field is set to "0", then there are no Transmit-

Section related interrupts awaiting service. Con-

versely, if this bit-field is set to "1", then there is at

least one Transmit Section related interrupt, awaiting

service.

NOTE: If this bit-field is set to "1", then the

µC/µP must

read the Source-Level Interrupt Status register, in order to

clear this bit-field.

Bit 0 - One-Second Interrupt Status

This Reset-upon-Read bit field indicates whether or

not a One-Second interrupt has been requested and

is awaiting service.

If this bit-field is set to "0", then the One-Second inter-

rupt is not awaiting service. Conversely, if this bit-

field is set to "1", then the One-Second interrupt is

awaiting service.

NOTE: This bit-field will be cleared immediately after the

µC/µP has read this register.

Receive DS3 Framer Configuration Registers

2.3.2.7

Receive DS3 Configuration & Status

Bit 7 - RxAIS (Receive AIS Pattern) Indicator

This Read-Only bit-field indicates whether or not the

Receive Section of the XRT7250 is currently receiv-

ing an AIS pattern or not.

BLOCK INTERRUPT STATUS REGISTER (ADDRESS = 0X05)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

RxDS3/E3

Interrupt

Status

Not Used

TxDS3/E3

Interrupt

Status

One-Second

Interrupt

Status

RUR

0000

000

RXDS3 CONFIGURATION & STATUS REGISTER (ADDRESS = 0X10)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

RxAIS

RxLOS

RxIdle

RxOOF

Reserved

Framing On

Parity

FSync

Algo

MSync

Algo

R/W

0000

000

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