XRT7250 datasheet(81/463 Pages) EXAR

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XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

Bit 3 - FERF Interrupt Enable

This Read/Write bit-field is used to enable or disable

the Change in FERF (Far End Receive Failure) Sta-

tus interrupt. Setting this bit-field to "1" enables this

interrupt. Setting this bit-field to "0" disables this in-

terrupt.

NOTE: For more information on Far-End Receive Failures

(or Yellow Alarms) please see Section 3.3.2.5.4.

Bit 2 - AIC Interrupt Enable

This Read/Write bit field allows the user to enable or

disable the Change in AIC value interrupt. Setting

this bit-field to "1" enables this interrupt. Setting this

bit-field to "0" disables this interrupt.

NOTE: For more information on this interrupt condition,

please see Section 3.3.2.5.6.

Bit 1 - OOF Interrupt Enable

This Read/Write bit field is used to enable or disable

the Change in Out-of-Frame (OOF) status interrupt.

Setting this bit-field to "1" enables this interrupt. Set-

ting this bit-field to "0" disables this interrupt.

NOTE: For more information on the OOF' Condition, please

see Section 3.3.2.2.

Bit 0 - P-Bit Error Interrupt Enable

This Read/Write bit-field is used to enable or disable

the P-Bit Error Detection interrupt. Setting this bit-

field to "1" enables this interrupt. Setting this bit-field

to "0" disables this interrupt.

NOTE: For more information on the P-Bit Error Checking/

Detection, please see Section 3.3.2.6.1.

2.3.2.10 Receive DS3 Interrupt Status Register

Bit 7 - CP Bit Error Interrupt Status

This Reset-upon-Read bit-field indicates whether or

not the CP Bit Error Interrupt has occurred since the

last read of this register. This bit-field will be “0” if the

Detection of CP-Bit Error Interrupt has not occurred

since the last read of this register. Conversely, this

bit-field will be set to “1” if this interrupt has occurred

since the last read of this register. The Detection of

CP Bit Error Interrupt will occur if the Receive DS3

Framer block detects a “CP” bit-error in the incoming

DS3 frame.

Bit 6 - LOS Interrupt Status

This Reset Upon Read bit will be set to "1", if the Re-

ceive DS3 Framer has detected a

Change in the LOS Status condition, since the last

time this register was read. This bit-field will be as-

serted under either of the following two conditions:

1. When the Receive DS3 Framer detects the

occurrence of an LOS Condition (e.g., the occur-

rence of 180 consecutive spaces in the incoming

DS3 data stream), and

2. When the Receive DS3 Framer detects the end

of an LOS Condition (e.g., when the Receive DS3

Framer detects 60 mark pulses in the last 180 bit

periods).

The local µP can determine the current state of the

LOS condition by reading bit 6 of the Rx DS3 Config-

uration and Status Register (Address = 0x10).

NOTE: For more information in the LOS of Signal (LOS)

Alarm, please see Section 3.3.2.5.1.

Bit 5 - AIS Interrupt Status

This Reset Upon Read bit field will be set to "1", if the

Receive DS3 Framer has detected a Change in the

AIS condition, since the last time this register was

read. This bit-field will be asserted under either of the

following two conditions:

1. When the Receive DS3 Framer first detects an

AIS Condition in the incoming DS3 data stream,

and

2. When the Receive DS3 Framer has detected the

end of an AIS Condition.

The local µP can determine the current state of the

AIS condition by reading bit 7 of the Rx DS3 Configu-

ration and Status Register (Address = 0x10).

NOTE: For more information on the AIS Condition please

see Sections 3.3.2.5.2.

Bit 4 - Idle Interrupt Status

This Reset Upon Read bit-field is set to "1" when the

Receive DS3 Framer detects a Change in the Idle

Condition in the incoming DS3 data stream. Specifi-

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13)

BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0

CP-Bit Error

Interrupt

Status

LOS

Interrupt

Status

AIS

Interrupt

Status

Idle Interrupt

Status

FERF

Interrupt

Status

AIC

Interrupt

Status

OOF

Interrupt

Status

P-Bit Error

Interrupt

Status

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