XRT7250 datasheet(55/463 Pages) EXAR

55 / 463 page

XRT7250

DS3/E3 FRAMER IC

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REV. 1.1.1

2.0

THE MICROPROCESSOR INTERFACE

BLOCK

The Microprocessor Interface section supports com-

munication between the local microprocessor (µP)

and the Framer IC. In particular, the Microprocessor

Interface section supports the following operations

between the local microprocessor and the Framer.

• The writing of configuration data into the Framer

on-chip (addressable) registers.

• The writing of an outbound PMDL (Path Mainte-

nance Data Link) message into the Transmit LAPD

Message buffer (within the Framer IC).

• The Framer IC's generation of an Interrupt Request

to the µP.

• The µP's servicing of the interrupt request from the

Framer IC.

• The monitoring of the system's health by periodi-

cally reading the on-chip Performance Monitor reg-

isters.

• The reading of an inbound PMDL Message from

the Receive LAPD Message Buffer (within the

Framer IC).

Each of these operations (between the local micro-

processor and the Framer IC) will be discussed in

some detail, throughout this data sheet.

Figure 24 presents a simple block diagram of the Mi-

croprocessor Interface Section, within the Framer IC.

2.1

THE MICROPROCESSOR INTERFACE BLOCK SIG-

NAL

The Framer IC may be configured into a wide variety

of different operating modes and have its perfor-

mance monitored by software through a standard (lo-

cal housekeeping) microprocessor, using data, ad-

dress and control signals.

The local µP configures the Framer IC (into a desired

operating mode) by writing data into specific address-

able, on-chip Read/Write registers, or on-chip RAM.

The microprocessor interface provides the signals

which are required for a general purpose micropro-

cessor to read or write data into these registers. The

Microprocessor Interface also supports polled and in-

terrupt driven environments. These interface signals

are described below in Table 1, Table 2, and Table 3.

The microprocessor interface can be configured to

operate in the Motorola Mode or in the Intel mode.

When the Microprocessor Interface is operating in the

Motorola mode, then some of the control signals

function in a manner as required by the Motorola

68000 family of microprocessors. Likewise, when the

Microprocessor Interface is operating in the Intel

Mode, then some of these Control Signals function in

a manner as required by the Intel 80xx family of mi-

croprocessors.

Table 1 lists and describes those Microprocessor In-

terface signals whose role is constant across the two

modes. Table 2 describes the role of some of these

signals when the Microprocessor Interface is operat-

ing in the Intel Mode. Likewise, Table 3 describes the

role of these signals when the Microprocessor Inter-

face is operating in the Motorola Mode.

FIGURE 24. SIMPLE BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK, WITHIN THE FRAMER IC

A[8:0]

WR_RW

Rd_DS

ALE_AS

Reset

Int

D[7:0]

MOTO

RDY_DTCK

Microprocessor

and

Programmable

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