XRT7250 datasheet(67/463 Pages) EXAR

67 / 463 page

XRT7250

DS3/E3 FRAMER IC

áç

REV. 1.1.1

A.1

Assert the ALE_AS (AS*) input pin by toggling

it "Low". This step enables the Address Bus

input drivers (within the XRT7250 DS3/E3

Framer) within the Framer Microprocessor

Interface Block.

A.2

Place the address of the initial target register or

buffer location (within the Framer), on the

Address Bus input pins, A[8:0].

A.3

At the same time, the Address-Decoding cir-

cuitry (within the user's system) should assert

the CS (Chip Select) input pins of the Framer

by toggling it "Low". This action enables further

communication between the µC/µP and the

Framer Microprocessor Interface block.

A.4

After allowing the data on the Address Bus pins

to settle (by waiting the appropriate Address

Setup time), the µC/µP should toggle the

ALE_AS input pin "High". This step causes the

Framer device to latch the contents of the

Address Bus into its internal circuitry. At this

point, the initial address of the burst access has

now been selected.

A.5

Further, the µC/µP should indicate that this

cycle is a Read cycle by setting the WR_RW

(R/W*) input pin "High".

A.6

Next the µC/µP should initiate the current bus

cycle by toggling the RD_DS (Data Strobe)

input pin "Low". This step will enable the bi-

directional data bus output drivers, within the

XRT7250 DS3/E3 Framer device. At this point,

the bi-directional data bus output drivers will

proceed to driver the contents of the Address

A.7

After some settling time, the data on the bi-

directional data bus will stabilize and can be

read by the µC/µP. The XRT7250 DS3/E3

Framer will indicate that this data can be read

by asserting the RDY_DTCK (DTACK) signal.

A.8

After the µC/µP detects the RDY_DTCK signal

(from the XRT7250 DS3/E3 Framer) it will ter-

minate the Read Cycle by toggling the RD_DS

(Data Strobe) input pin "High".

Figure 33 presents an illustration of the behavior of

the Microprocessor Interface Signals during the initial

Read Operation, within a Burst I/O Cycle, for a Motor-

ola-type µC/µP.

At the completion of this initial read cycle, the µC/µP

has read in the contents of the first register or buffer

location (within the XRT7250 DS3/E3 Framer) for this

particular burst access operation. In order to illus-

trate how this burst I/O cycle works, the byte (or word)

of data, that is being read in Figure 33 has been la-

beled Valid Data at Offset = 0x00. This indicates that

the µC/µP is reading the very first register (or buffer

location) in this burst access.

2.2.2.2.2.1.2

The Subsequent Read Operations

The procedure that the µC/µP must use to perform

the remaining read cycles, within this Burst Access

operation, is presented below.

B.0

Execute each subsequent Read Cycle, as

described in steps B.1 through B.3, below.

B.1

Without toggling the ALE_AS input pin (e.g.,

keeping it "High"), toggle the RD_DS (Data

Strobe) input pin "Low". This step accom-

plishes the following.

FIGURE 33. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING THE INITIAL READ OPERATION OF A

BURST CYCLE (MOTOROLA TYPE PROCESSOR)

ALE_AS

RD_DS

A[8:0]

D[15:0]

Rdy_Dtck

Not Valid

Valid Data at Offset = 0x00

Address of “Initial” Target Register (Offset = 0x00)

WR_RW

XRT7250 датащи(PDF) 67 Page - Exar Corporation

XRT7250 датащи(HTML) 67 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL