TMS320DM643 datasheet(121/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 5-42. Switching Characteristics Over Recommended Operating Conditions for McBSP

(1) (2)

(see Figure 5-46)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

tc(CKRX)

Cycle time, CLKR/X

CLKR/X int

4P or 6.67(3)(4)(5)

tw(CKRX)

Pulse duration, CLKR/X high or CLKR/X low

CLKR/X int

C – 1(6)

C + 1(6)

td(CKRH-FRV)

Delay time, CLKR high to internal FSR valid

CLKR int

–2.1

CLKX int

–1.7

td(CKXH-FXV)

Delay time, CLKX high to internal FSX valid

CLKX ext

1.7

CLKX int

–3.9

Disable time, DX high impedance following last data

tdis(CKXH-DXHZ)

bit from CLKX high

CLKX ext

2.0

CLKX int

–3.9 + D1(7)

4 + D2(7)

td(CKXH-DXV)

Delay time, CLKX high to DX valid

CLKX ext

2.0 + D1(7)

9 + D2(7)

Delay time, FSX high to DX valid

FSX int

–2.3 + D1(8)

5.6 + D2(8)

td(FXH-DXV)

ONLY applies when in data

FSX ext

1.9 + D1(8)

9 + D2(8)

delay 0 (XDATDLY = 00b) mode

(1)

CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also

inverted.

(2)

Minimum delay times also represent minimum output hold times.

(3)

Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times

are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.

(4)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(5)

Use whichever value is greater.

(6)

The CLKSM bit in the SRGR0 register must remain a 1, the DM643 device does not support a CLKS input.

C = H or L

H = CLKX high pulse width = (CLKGDV/2 + 1) * 4P if CLKGDV is even

H = CLKX high pulse width = (CLKGDV + 1)/2 * 4P if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * 4P if CLKGDV is even

L = CLKX low pulse width = (CLKGDV + 1)/2 * 4P if CLKGDV is odd or zero

CLKGDV should be set appropriately to ensure the McBSP bit rate does not exceed the maximum limit (see footnote (4) above).

(7)

Extra delay from CLKX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

(8)

Extra delay from FSX high to DX valid applies only to the first data bit of a device, if and only if DXENA = 1 in SPCR.

if DXENA = 0, then D1 = D2 = 0

if DXENA = 1, then D1 = 4P, D2 = 8P

121

DM643 Peripheral Information and Electrical Specifications

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