TMS320DM643 datasheet(123/160 Pages) TI

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Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

Bit 0

Bit(n-1)

(n-2)

(n-3)

(n-4)

CLKX

FSX

TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 5-44. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI

Master or Slave: CLKSTP = 10b, CLKXP = 0

(1) (2) (see Figure 5-47)

–500

–600

NO.

PARAMETER

UNIT

MASTER(3)

SLAVE

MIN

MAX

MIN

MAX

th(CKXL-FXL)

Hold time, FSX low after CLKX low(4)

T – 2

T + 3

td(FXL-CKXH)

Delay time, FSX low to CLKX high(5)

L – 2.5

L + 3

td(CKXH-DXV)

Delay time, CLKX high to DX valid

–2

12P + 2.8

20P + 17

Disable time, DX high impedance following last data bit

tdis(CKXL-DXHZ)

L – 2

L + 3

from CLKX low

Disable time, DX high impedance following last data bit

tdis(FXH-DXHZ)

4P + 3

12P + 17

from FSX high

td(FXL-DXV)

Delay time, FSX low to DX valid

8P + 1.8

16P + 17

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(2)

For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

(3)

The CLKSM bit in the SRGR0 register must remain a 1, the DM643 device does not support a CLKS input.

T = CLKX period = (1 + CLKGDV) * 4P

H = CLKX high pulse width = (CLKGDV/2 + 1) * 4P if CLKGDV is even

H = CLKX high pulse width = (CLKGDV + 1)/2 * 4P if CLKGDV is odd or zero

L = CLKX low pulse width = (CLKGDV/2) * 4P if CLKGDV is even

L = CLKX low pulse width = (CLKGDV + 1)/2 * 4P if CLKGDV is odd or zero

(4)

FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input

on FSX and FSR is inverted before being used internally.

CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP

CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP

(5)

FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master

clock (CLKX).

Figure 5-47. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

Table 5-45. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

(1) (2)

(see Figure 5-48)

–500

–600

NO.

UNIT

MASTER

SLAVE

MIN

MAX

MIN

MAX

tsu(DRV-CKXH)

Setup time, DR valid before CLKX high

2 – 12P

th(CKXH-DRV)

Hold time, DR valid after CLKX high

5 + 24P

(1)

P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns.

(2)

For all SPI Slave modes, CLKG is programmed as 1/4 of the CPU clock by setting CLKSM = CLKGDV = 1.

123

DM643 Peripheral Information and Electrical Specifications

TMS320DM643 датащи(PDF) 123 Page - Texas Instruments

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