TMS320DM643 datasheet(89/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

5.8.3.2

Programmable Synchronous Interface Timing

Table 5-23. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module

(see Figure 5-19)

–500

–600

NO.

UNIT

MIN

MAX

MIN

MAX

tsu(EDV-EKOxH)

Setup time, read AEDx valid before AECLKOUTx high

3.1

th(EKOxH-EDV)

Hold time, read AEDx valid after AECLKOUTx high

1.5

Table 5-24. Switching Characteristics Over Recommended Operating Conditions for Programmable

Synchronous Interface Cycles for EMIFA Module

(1) (see Figure 5-19– Figure 5-21)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(EKOxH-CEV)

Delay time, AECLKOUTx high to ACEx valid

1.3

6.4

1.3

4.9

td(EKOxH-BEV)

Delay time, AECLKOUTx high to ABEx valid

6.4

4.9

td(EKOxH-BEIV)

Delay time, AECLKOUTx high to ABEx invalid

1.3

td(EKOxH-EAV)

Delay time, AECLKOUTx high to AEAx valid

6.4

4.9

td(EKOxH-EAIV)

Delay time, AECLKOUTx high to AEAx invalid

1.3

td(EKOxH-ADSV)

Delay time, AECLKOUTx high to ASADS/ASRE valid

1.3

6.4

1.3

4.9

td(EKOxH-OEV)

Delay time, AECLKOUTx high to ASOE valid

1.3

6.4

1.3

4.9

td(EKOxH-EDV)

Delay time, AECLKOUTx high to AEDx valid

6.4

4.9

td(EKOxH-EDIV)

Delay time, AECLKOUTx high to AEDx invalid

1.3

td(EKOxH-WEV)

Delay time, AECLKOUTx high to ASWE valid

1.3

6.4

1.3

4.9

(1)

The following parameters are programmable via the EMIF CE Space Secondary Control register (CExSEC):

•

Read latency (SYNCRL): 0-, 1-, 2-, or 3-cycle read latency

•

Write latency (SYNCWL): 0-, 1-, 2-, or 3-cycle write latency

•

ACEx assertion length (CEEXT): For standard SBSRAM or ZBT SRAM interface, ACEx goes inactive after the final command has

been issued (CEEXT = 0). For synchronous FIFO interface with glue, ACEx is active when ASOE is active (CEEXT = 1).

•

Function of ASADS/ASRE (RENEN): For standard SBSRAM or ZBT SRAM interface, ASADS/ASRE acts as ASADS with deselect

cycles (RENEN = 0). For FIFO interface, ASADS/ASRE acts as ASRE with NO deselect cycles (RENEN = 1).

•

Synchronization clock (SNCCLK): Synchronized to AECLKOUT1 or AECLKOUT2

DM643 Peripheral Information and Electrical Specifications

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