TMS320DM643 datasheet(93/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

5.8.3.3

Synchronous DRAM Timing

Table 5-25. Timing Requirements for Synchronous DRAM Cycles for EMIFA Module (see Figure 5-22)

–500

–600

NO.

UNIT

MIN

MAX

MIN

MAX

tsu(EDV-EKO1H)

Setup time, read AEDx valid before AECLKOUTx high

2.1

0.6

th(EKO1H-EDV)

Hold time, read AEDx valid after AECLKOUTx high

2.5

1.8

Table 5-26. Switching Characteristics Over Recommended Operating Conditions for Synchronous DRAM

Cycles for EMIFA Module (see Figure 5-22– Figure 5-29)

–500

–600

NO.

PARAMETER

UNIT

MIN

MAX

MIN

MAX

td(EKO1H-CEV)

Delay time, AECLKOUTx high to ACEx valid

1.3

6.4

1.3

4.9

td(EKO1H-BEV)

Delay time, AECLKOUTx high to ABEx valid

6.4

4.9

td(EKO1H-BEIV)

Delay time, AECLKOUTx high to ABEx invalid

1.3

td(EKO1H-EAV)

Delay time, AECLKOUTx high to AEAx valid

6.4

4.9

td(EKO1H-EAIV)

Delay time, AECLKOUTx high to AEAx invalid

1.3

td(EKO1H-CASV)

Delay time, AECLKOUTx high to ASDCAS valid

1.3

6.4

1.3

4.9

td(EKO1H-EDV)

Delay time, AECLKOUTx high to AEDx valid

6.4

4.9

td(EKO1H-EDIV)

Delay time, AECLKOUTx high to AEDx invalid

1.3

td(EKO1H-WEV)

Delay time, AECLKOUTx high to ASDWE valid

1.3

6.4

1.3

4.9

td(EKO1H-RAS)

Delay time, AECLKOUTx high to ASDRAS valid

1.3

6.4

1.3

4.9

td(EKO1H-ACKEV)

Delay time, AECLKOUTx high to ASDCKE valid

1.3

6.4

1.3

4.9

td(EKO1H-PDTV)

Delay time, AECLKOUTx high to APDT valid

1.3

6.4

1.3

4.9

DM643 Peripheral Information and Electrical Specifications

TMS320DM643 датащи(PDF) 93 Page - Texas Instruments

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