TMS320DM643 datasheet(28/160 Pages) TI

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TMS320DM643

Video/Imaging Fixed-Point Digital Signal Processor

SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005

Table 2-4. Terminal Functions

SIGNAL

IPD/

TYPE(1)

DESCRIPTION

IPU(2)

NAME

NO.

CLOCK/PLL CONFIGURATION

CLKIN

AC2

Clock Input. This clock is the input to the on-chip PLL.

Clock output at 1/4 of the device speed (O/Z) [default] or this pin can be

CLKOUT4/GP0[1](3)

I/O/Z

IPU

programmed as a GP0 1 pin (I/O/Z).

Clock output at 1/6 of the device speed (O/Z) [default] or this pin can be

CLKOUT6/GP0[2](3)

I/O/Z

IPU

programmed as a GP0 2 pin (I/O/Z).

CLKMODE1

AE4

IPD

Clock mode select

•

Selects whether the CPU clock frequency = input clock frequency x1

(Bypass), x6, or x12.

CLKMODE0

AA2

IPD

For more details on the CLKMODE pins and the PLL multiply factors, see

the Clock PLL section of this data sheet.

PLLV(4)

A(1)

PLL voltage supply

JTAG EMULATION

TMS

E15

IPU

JTAG test-port mode select

TDO

B18

O/Z

IPU

JTAG test-port data out

TDI

A18

IPU

JTAG test-port data in

TCK

A16

IPU

JTAG test-port clock

JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1

TRST

D14

IPD

JTAG compatibility statement portion of this data sheet.

EMU11

D17

I/O/Z

IPU

Emulation pin 11. Reserved for future use, leave unconnected.

EMU10

C17

I/O/Z

IPU

Emulation pin 10. Reserved for future use, leave unconnected.

EMU9

B17

I/O/Z

IPU

Emulation pin 9. Reserved for future use, leave unconnected.

EMU8

D16

I/O/Z

IPU

Emulation pin 8. Reserved for future use, leave unconnected.

EMU7

A17

I/O/Z

IPU

Emulation pin 7. Reserved for future use, leave unconnected.

EMU6

C16

I/O/Z

IPU

Emulation pin 6. Reserved for future use, leave unconnected.

EMU5

B16

I/O/Z

IPU

Emulation pin 5. Reserved for future use, leave unconnected.

EMU4

D15

I/O/Z

IPU

Emulation pin 4. Reserved for future use, leave unconnected.

EMU3

C15

I/O/Z

IPU

Emulation pin 3. Reserved for future use, leave unconnected.

EMU2

B15

I/O/Z

IPU

Emulation pin 2. Reserved for future use, leave unconnected.

EMU1

C14

I/O/Z

IPU

Emulation pin 1 (5)

EMU0

A15

I/O/Z

IPU

Emulation pin 0 (5)

RESETS, INTERRUPTS, AND GENERAL-PURPOSE INPUT/OUTPUTS

RESET

Device reset

Nonmaskable interrupt, edge-driven (rising edge)

Note: Any noise on the NMI pin may trigger an NMI interrupt; therefore, if the

NMI

IPD

NMI pin is not used, it is recommended that the NMI pin be grounded versus

relying on the IPD.

GP0[7]/EXT_INT7

I/O/Z

IPU

General-purpose input/output (GPIO) pins (I/O/Z) or external interrupts (input

only). The default after reset setting is GPIO enabled as input-only.

GP0[6]/EXT_INT6

I/O/Z

IPU

•

When these pins function as External Interrupts [by selecting the

GP0[5]/EXT_INT5

I/O/Z

IPU

corresponding interrupt enable register bit (IER.[7:4])], they are edge-driven

and the polarity can be independently selected via the External Interrupt

GP0[4]/EXT_INT4

I/O/Z

IPU

Polarity Register bits (EXTPOL.[3:0]).

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal

(2)

IPD = Internal pulldown, IPU = Internal pullup. (These IPD/IPU signal pins feature a 30-k

Ω IPD or IPU resistor. To pull up a signal to the

opposite supply rail, a 1-k

Ω resistor should be used.)

(3)

These pins are multiplexed pins. For more details, see the Device Configurations section of this data sheet.

(4)

PLLV is not part of external voltage supply. See the Clock PLL section for information on how to connect this pin.

(5)

The EMU0 and EMU1 pins are internally pulled up with 30-k

Ω resistors; therefore, for emulation and normal operation, no external

pullup/pulldown resistors are necessary. However, for boundary scan operation, pull down the EMU1 and EMU0 pins with a dedicated

1-k

Ω resistor.

Device Overview

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