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TMS320DM643 датащи(PDF) 77 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 77 Page - Texas Instruments |
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77 / 160 page ![]() www.ti.com TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005 Table 5-11. Switching Characteristics Over Recommended Operating Conditions During Reset (1) (2) (3) (see Figure 5-9) –500 –600 NO. PARAMETER UNIT MIN MAX 2 td(RSTL-ECKI) Delay time, RESET low to AECLKIN synchronized internally 2E 3P + 20E ns 3 td(RSTH-ECKI) Delay time, RESET high to AECLKIN synchronized internally 2E 8P + 20E ns 4 td(RSTL-ECKO1HZ) Delay time, RESET low to AECLKOUT1 high impedance 2E ns 5 td(RSTH-ECKO1V) Delay time, RESET high to AECLKOUT1 valid 8P + 20E ns 6 td(RSTL-EMIFZHZ) Delay time, RESET low to EMIF Z high impedance 2E 3P + 4E ns 7 td(RSTH-EMIFZV) Delay time, RESET high to EMIF Z valid 16E 8P + 20E ns 8 td(RSTL-EMIFHIV) Delay time, RESET low to EMIF high group invalid 2E ns 9 td(RSTH-EMIFHV) Delay time, RESET high to EMIF high group valid 8P + 20E ns 10 td(RSTL-EMIFLIV) Delay time, RESET low to EMIF low group invalid 2E ns 11 td(RSTH-EMIFLV) Delay time, RESET high to EMIF low group valid 8P + 20E ns 14 td(RSTL-ZHZ) Delay time, RESET low to Z group high impedance 0 ns 15 td(RSTH-ZV) Delay time, RESET high to Z group valid 2P 8P ns (1) P = 1/CPU clock frequency in ns. For example, when running parts at 600 MHz, use P = 1.67 ns. (2) E = the EMIF input clock (AECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA. (3) EMIF Z group consists of: AEA[22:3], AED[63:0], ACE[3:0], ABE[7:0], AARE/ASDCAS/ASADS/ASRE, AAWE/ASDWE/ASWE, AAOE/ASDRAS/ASOE, ASOE3, ASDCKE, and APDT EMIF high group consists of: AHOLDA (when the corresponding HOLD input is high) EMIF low group consists of: ABUSREQ; AHOLDA (when the corresponding HOLD input is low) Z group consists of: HD[31:0] and the muxed EMAC output pins, MDCLK, MDIO, CLKX0, FSX0, DX0, CLKR0, FSR0, TOUT0, TOUT1, VDAC/GP0[8], GP0[13, 11, 10, 7:0], HR/W, HDS2, HDS1, HCS, HCNTL1, HAS, HCNTL0, HHWIL (16-bit HPI mode only), HRDY, HINT, VP1D[19:0], and VP2D[19:0]. 77 DM643 Peripheral Information and Electrical Specifications |
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