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TMS320DM643 датащи(PDF) 15 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 15 Page - Texas Instruments |
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15 / 160 page ![]() www.ti.com 2.3.1 L2 Architecture Expanded 0x0000 0000 011 010 001 111 0x0002 0000 000 L2MODE L2 Memory Block Base Address 0x0003 8000 0x0003 0000 0x0004 0000 128K-Byte SRAM 64K-Byte RAM 32K-Byte RAM 0x0003 FFFF 32K-Byte RAM TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005 Figure 2-2 shows the detail of the L2 architecture on the TMS320DM643 device. For more information on the L2MODE bits, see the cache configuration (CCFG) register bit field descriptions in the TMS320C64x Two-Level Internal Memory Reference Guide (literature number SPRU610). Figure 2-2. TMS320DM643 L2 Architecture Memory Configuration Device Overview 15 |
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