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TMS320DM643 датащи(PDF) 25 Page - Texas Instruments |
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TMS320DM643 датащи(HTML) 25 Page - Texas Instruments |
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25 / 160 page ![]() www.ti.com VP1D[10] VP1D[11] VP1D[12]/AXR0[0] VP1D[13]/AXR0[1] VP1D[14]/AXR0[2] VP1D[15]/AXR0[3] VP1D[16]/AXR0[4] VP1D[17]/AXR0[5] VP1D[0] VP1D[1] VP1D[2] VP1D[3] VP1D[4] VP1D[5] VP1D[6] VP1D[7] VP1D[8] VP1D[9] VP1D[18]/AXR0[6] VP1D[19]/AXR0[7] Capture/Display Buffer (2560 Bytes) VP1CLK0 VP1CLK1 VP1CTL0 VP1CTL1 VP1CTL2 Timing and Control Logic Video Port 1 (VP1) Channel B(B) Channel A(A) Capture/Display Buffer (2560 Bytes) Channel B uses only the VP1D[19:10] bidirectional pins STCLK(C) A. Channel A supports: BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) display modes and BT.656 (8/10-bit), Y/C Video (16/20-bit), RAW Video (16/20-bit) capture modes [TSI (8-bit) capture mode − currently not supported]. B. Channel B supports: BT.656 (8/10-bit), RAW Video (8/10-bit) capture modes and can display synchronized RAW Video data with Channel A. C. The same STCLK signal is used for both video ports (VP1 and VP2). TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor SPRS269A – FEBRUARY 2005 – REVISED APRIL 2005 Figure 2-12. Video Port 1 Peripheral Signals Device Overview 25 |
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